[PATCH] D73643: [WIP] Macro Fusion for RISC-V

[Sam Elliott via Phabricator via llvm-commits]

lenary added a comment.

Wow, this is really cool! I'm amazed it took so little (target-specific) code.

It would be good to understand the trade-offs of doing this rescheduling when the core doesn't necessarily support fusion. With the current instructions, I don't see many scheduling problems coming from blindly fusing all the time, but maybe this should be a subtarget feature that can be switched on and off in case it creates scheduling issues.



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Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:125
+  createMachineScheduler(MachineSchedContext *C) const override {
+    ScheduleDAGMILive *DAG = createGenericSchedLive(C);
+    DAG->addMutation(createRISCVMacroFusionDAGMutation());
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Is this the default kind of machine scheduler? Does it necessarily make sense to schedule by liveness when RISC-V has so many registers?


Repository:
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https://reviews.llvm.org/D73643