[llvm] d3cea95 - AMDGPU/GlobalISel: Fix tests in release build
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 29 12:27:27 PST 2020
Author: Matt Arsenault
Date: 2020-01-29T12:27:16-08:00
New Revision: d3cea95475756e1d08cdfe40dd8df8bc4b4eec22
URL: https://github.com/llvm/llvm-project/commit/d3cea95475756e1d08cdfe40dd8df8bc4b4eec22
DIFF: https://github.com/llvm/llvm-project/commit/d3cea95475756e1d08cdfe40dd8df8bc4b4eec22.diff
LOG: AMDGPU/GlobalISel: Fix tests in release build
Irritatingly the failure output is different in release vs. debug
because of the legality check is removed without asserts, so a register
ends up constrained only in release builds.
Added:
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.s96.mir
Modified:
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
index 25e5790c06cb..3c25f2800344 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
@@ -6,11 +6,10 @@
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX10 %s
-# FIXME: global with MUBUF
-
---
name: load_global_s32_from_4
+
legalized: true
regBankSelected: true
tracksRegLiveness: true
@@ -243,64 +242,6 @@ body: |
---
-name: load_global_v3s32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1
-
- ; GFX6-LABEL: name: load_global_v3s32
- ; GFX6: liveins: $vgpr0_vgpr1
- ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
- ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
- ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
- ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GFX6: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
- ; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3
- ; GFX6: [[BUFFER_LOAD_DWORDX3_ADDR64_:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX3_ADDR64 [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 12, align 4, addrspace 1)
- ; GFX6: $vgpr0_vgpr1_vgpr2 = COPY [[BUFFER_LOAD_DWORDX3_ADDR64_]]
- ; GFX7-LABEL: name: load_global_v3s32
- ; GFX7: liveins: $vgpr0_vgpr1
- ; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
- ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
- ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
- ; GFX7: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
- ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3
- ; GFX7: [[BUFFER_LOAD_DWORDX3_ADDR64_:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX3_ADDR64 [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 12, align 4, addrspace 1)
- ; GFX7: $vgpr0_vgpr1_vgpr2 = COPY [[BUFFER_LOAD_DWORDX3_ADDR64_]]
- ; GFX7-FLAT-LABEL: name: load_global_v3s32
- ; GFX7-FLAT: liveins: $vgpr0_vgpr1
- ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
- ; GFX7-FLAT: [[FLAT_LOAD_DWORDX3_:%[0-9]+]]:vreg_96 = FLAT_LOAD_DWORDX3 [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 12, align 4, addrspace 1)
- ; GFX7-FLAT: $vgpr0_vgpr1_vgpr2 = COPY [[FLAT_LOAD_DWORDX3_]]
- ; GFX8-LABEL: name: load_global_v3s32
- ; GFX8: liveins: $vgpr0_vgpr1
- ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
- ; GFX8: [[FLAT_LOAD_DWORDX3_:%[0-9]+]]:vreg_96 = FLAT_LOAD_DWORDX3 [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 12, align 4, addrspace 1)
- ; GFX8: $vgpr0_vgpr1_vgpr2 = COPY [[FLAT_LOAD_DWORDX3_]]
- ; GFX9-LABEL: name: load_global_v3s32
- ; GFX9: liveins: $vgpr0_vgpr1
- ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
- ; GFX9: [[GLOBAL_LOAD_DWORDX3_:%[0-9]+]]:vreg_96 = GLOBAL_LOAD_DWORDX3 [[COPY]], 0, 0, 0, 0, implicit $exec :: (load 12, align 4, addrspace 1)
- ; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[GLOBAL_LOAD_DWORDX3_]]
- ; GFX10-LABEL: name: load_global_v3s32
- ; GFX10: liveins: $vgpr0_vgpr1
- ; GFX10: $vcc_hi = IMPLICIT_DEF
- ; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
- ; GFX10: [[GLOBAL_LOAD_DWORDX3_:%[0-9]+]]:vreg_96 = GLOBAL_LOAD_DWORDX3 [[COPY]], 0, 0, 0, 0, implicit $exec :: (load 12, align 4, addrspace 1)
- ; GFX10: $vgpr0_vgpr1_vgpr2 = COPY [[GLOBAL_LOAD_DWORDX3_]]
- %0:vgpr(p1) = COPY $vgpr0_vgpr1
- %1:vgpr(<3 x s32>) = G_LOAD %0 :: (load 12, align 4, addrspace 1)
- $vgpr0_vgpr1_vgpr2 = COPY %1
-
-...
-
----
-
name: load_global_v4s32
legalized: true
regBankSelected: true
@@ -502,53 +443,6 @@ body: |
---
-name: load_global_s96
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1
-
- ; GFX6-LABEL: name: load_global_s96
- ; GFX6: liveins: $vgpr0_vgpr1
- ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX6: [[LOAD:%[0-9]+]]:vreg_96(s96) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
- ; GFX6: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](s96)
- ; GFX7-LABEL: name: load_global_s96
- ; GFX7: liveins: $vgpr0_vgpr1
- ; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX7: [[LOAD:%[0-9]+]]:vreg_96(s96) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
- ; GFX7: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](s96)
- ; GFX7-FLAT-LABEL: name: load_global_s96
- ; GFX7-FLAT: liveins: $vgpr0_vgpr1
- ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX7-FLAT: [[LOAD:%[0-9]+]]:vreg_96(s96) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
- ; GFX7-FLAT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](s96)
- ; GFX8-LABEL: name: load_global_s96
- ; GFX8: liveins: $vgpr0_vgpr1
- ; GFX8: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX8: [[LOAD:%[0-9]+]]:vreg_96(s96) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
- ; GFX8: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](s96)
- ; GFX9-LABEL: name: load_global_s96
- ; GFX9: liveins: $vgpr0_vgpr1
- ; GFX9: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX9: [[LOAD:%[0-9]+]]:vreg_96(s96) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
- ; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](s96)
- ; GFX10-LABEL: name: load_global_s96
- ; GFX10: liveins: $vgpr0_vgpr1
- ; GFX10: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX10: [[LOAD:%[0-9]+]]:vreg_96(s96) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
- ; GFX10: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](s96)
- %0:vgpr(p1) = COPY $vgpr0_vgpr1
- %1:vgpr(s96) = G_LOAD %0 :: (load 12, align 4, addrspace 1)
- $vgpr0_vgpr1_vgpr2 = COPY %1
-
-...
-
----
-
name: load_global_s128
legalized: true
regBankSelected: true
@@ -882,53 +776,6 @@ body: |
---
-name: load_global_v6s16
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1
-
- ; GFX6-LABEL: name: load_global_v6s16
- ; GFX6: liveins: $vgpr0_vgpr1
- ; GFX6: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX6: [[LOAD:%[0-9]+]]:vgpr(<6 x s16>) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
- ; GFX6: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<6 x s16>)
- ; GFX7-LABEL: name: load_global_v6s16
- ; GFX7: liveins: $vgpr0_vgpr1
- ; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX7: [[LOAD:%[0-9]+]]:vreg_96(<6 x s16>) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
- ; GFX7: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<6 x s16>)
- ; GFX7-FLAT-LABEL: name: load_global_v6s16
- ; GFX7-FLAT: liveins: $vgpr0_vgpr1
- ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX7-FLAT: [[LOAD:%[0-9]+]]:vreg_96(<6 x s16>) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
- ; GFX7-FLAT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<6 x s16>)
- ; GFX8-LABEL: name: load_global_v6s16
- ; GFX8: liveins: $vgpr0_vgpr1
- ; GFX8: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX8: [[LOAD:%[0-9]+]]:vreg_96(<6 x s16>) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
- ; GFX8: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<6 x s16>)
- ; GFX9-LABEL: name: load_global_v6s16
- ; GFX9: liveins: $vgpr0_vgpr1
- ; GFX9: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX9: [[LOAD:%[0-9]+]]:vreg_96(<6 x s16>) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
- ; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<6 x s16>)
- ; GFX10-LABEL: name: load_global_v6s16
- ; GFX10: liveins: $vgpr0_vgpr1
- ; GFX10: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
- ; GFX10: [[LOAD:%[0-9]+]]:vreg_96(<6 x s16>) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
- ; GFX10: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<6 x s16>)
- %0:vgpr(p1) = COPY $vgpr0_vgpr1
- %1:vgpr(<6 x s16>) = G_LOAD %0 :: (load 12, align 4, addrspace 1)
- $vgpr0_vgpr1_vgpr2 = COPY %1
-
-...
-
----
-
name: load_global_v8s16
legalized: true
regBankSelected: true
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.s96.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.s96.mir
new file mode 100644
index 000000000000..f2beb1dddcdd
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.s96.mir
@@ -0,0 +1,138 @@
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7 %s
+# RUN: llc -march=amdgcn -mcpu=hawaii -mattr=+flat-for-global -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7-FLAT %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX10 %s
+
+---
+
+name: load_global_v3s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; GFX7-LABEL: name: load_global_v3s32
+ ; GFX7: liveins: $vgpr0_vgpr1
+ ; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; GFX7: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
+ ; GFX7: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GFX7: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
+ ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub3
+ ; GFX7: [[BUFFER_LOAD_DWORDX3_ADDR64_:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX3_ADDR64 [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 12, align 4, addrspace 1)
+ ; GFX7: $vgpr0_vgpr1_vgpr2 = COPY [[BUFFER_LOAD_DWORDX3_ADDR64_]]
+ ; GFX7-FLAT-LABEL: name: load_global_v3s32
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX7-FLAT: [[FLAT_LOAD_DWORDX3_:%[0-9]+]]:vreg_96 = FLAT_LOAD_DWORDX3 [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 12, align 4, addrspace 1)
+ ; GFX7-FLAT: $vgpr0_vgpr1_vgpr2 = COPY [[FLAT_LOAD_DWORDX3_]]
+ ; GFX8-LABEL: name: load_global_v3s32
+ ; GFX8: liveins: $vgpr0_vgpr1
+ ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX8: [[FLAT_LOAD_DWORDX3_:%[0-9]+]]:vreg_96 = FLAT_LOAD_DWORDX3 [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 12, align 4, addrspace 1)
+ ; GFX8: $vgpr0_vgpr1_vgpr2 = COPY [[FLAT_LOAD_DWORDX3_]]
+ ; GFX9-LABEL: name: load_global_v3s32
+ ; GFX9: liveins: $vgpr0_vgpr1
+ ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX9: [[GLOBAL_LOAD_DWORDX3_:%[0-9]+]]:vreg_96 = GLOBAL_LOAD_DWORDX3 [[COPY]], 0, 0, 0, 0, implicit $exec :: (load 12, align 4, addrspace 1)
+ ; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[GLOBAL_LOAD_DWORDX3_]]
+ ; GFX10-LABEL: name: load_global_v3s32
+ ; GFX10: liveins: $vgpr0_vgpr1
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX10: [[GLOBAL_LOAD_DWORDX3_:%[0-9]+]]:vreg_96 = GLOBAL_LOAD_DWORDX3 [[COPY]], 0, 0, 0, 0, implicit $exec :: (load 12, align 4, addrspace 1)
+ ; GFX10: $vgpr0_vgpr1_vgpr2 = COPY [[GLOBAL_LOAD_DWORDX3_]]
+ %0:vgpr(p1) = COPY $vgpr0_vgpr1
+ %1:vgpr(<3 x s32>) = G_LOAD %0 :: (load 12, align 4, addrspace 1)
+ $vgpr0_vgpr1_vgpr2 = COPY %1
+
+...
+
+---
+
+name: load_global_s96
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; GFX7-LABEL: name: load_global_s96
+ ; GFX7: liveins: $vgpr0_vgpr1
+ ; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; GFX7: [[LOAD:%[0-9]+]]:vreg_96(s96) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
+ ; GFX7: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](s96)
+ ; GFX7-FLAT-LABEL: name: load_global_s96
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; GFX7-FLAT: [[LOAD:%[0-9]+]]:vreg_96(s96) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
+ ; GFX7-FLAT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](s96)
+ ; GFX8-LABEL: name: load_global_s96
+ ; GFX8: liveins: $vgpr0_vgpr1
+ ; GFX8: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; GFX8: [[LOAD:%[0-9]+]]:vreg_96(s96) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
+ ; GFX8: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](s96)
+ ; GFX9-LABEL: name: load_global_s96
+ ; GFX9: liveins: $vgpr0_vgpr1
+ ; GFX9: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; GFX9: [[LOAD:%[0-9]+]]:vreg_96(s96) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
+ ; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](s96)
+ ; GFX10-LABEL: name: load_global_s96
+ ; GFX10: liveins: $vgpr0_vgpr1
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; GFX10: [[LOAD:%[0-9]+]]:vreg_96(s96) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
+ ; GFX10: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](s96)
+ %0:vgpr(p1) = COPY $vgpr0_vgpr1
+ %1:vgpr(s96) = G_LOAD %0 :: (load 12, align 4, addrspace 1)
+ $vgpr0_vgpr1_vgpr2 = COPY %1
+
+...
+
+---
+
+name: load_global_v6s16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; GFX7-LABEL: name: load_global_v6s16
+ ; GFX7: liveins: $vgpr0_vgpr1
+ ; GFX7: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; GFX7: [[LOAD:%[0-9]+]]:vreg_96(<6 x s16>) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
+ ; GFX7: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<6 x s16>)
+ ; GFX7-FLAT-LABEL: name: load_global_v6s16
+ ; GFX7-FLAT: liveins: $vgpr0_vgpr1
+ ; GFX7-FLAT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; GFX7-FLAT: [[LOAD:%[0-9]+]]:vreg_96(<6 x s16>) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
+ ; GFX7-FLAT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<6 x s16>)
+ ; GFX8-LABEL: name: load_global_v6s16
+ ; GFX8: liveins: $vgpr0_vgpr1
+ ; GFX8: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; GFX8: [[LOAD:%[0-9]+]]:vreg_96(<6 x s16>) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
+ ; GFX8: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<6 x s16>)
+ ; GFX9-LABEL: name: load_global_v6s16
+ ; GFX9: liveins: $vgpr0_vgpr1
+ ; GFX9: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; GFX9: [[LOAD:%[0-9]+]]:vreg_96(<6 x s16>) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
+ ; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<6 x s16>)
+ ; GFX10-LABEL: name: load_global_v6s16
+ ; GFX10: liveins: $vgpr0_vgpr1
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; GFX10: [[LOAD:%[0-9]+]]:vreg_96(<6 x s16>) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
+ ; GFX10: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<6 x s16>)
+ %0:vgpr(p1) = COPY $vgpr0_vgpr1
+ %1:vgpr(<6 x s16>) = G_LOAD %0 :: (load 12, align 4, addrspace 1)
+ $vgpr0_vgpr1_vgpr2 = COPY %1
+
+...
+
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