[llvm] 2ec9545 - Revert "[ARM] Fix data race on RegisterBank initialization."

[Huihui Zhang via llvm-commits]

Author: Huihui Zhang
Date: 2020-01-29T11:15:27-08:00
New Revision: 2ec954579a65b8adf9ec6fb99df40ad0c78a6ce1

URL: https://github.com/llvm/llvm-project/commit/2ec954579a65b8adf9ec6fb99df40ad0c78a6ce1
DIFF: https://github.com/llvm/llvm-project/commit/2ec954579a65b8adf9ec6fb99df40ad0c78a6ce1.diff

LOG: Revert "[ARM] Fix data race on RegisterBank initialization."

There looks to be buildbot failure related.

This reverts commit 91618d940ea3009d7e1489df4c8ca12017a0f612.

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
index 1138c4065f04..43c8cd5a89be 100644
--- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
@@ -131,47 +131,45 @@ static void checkValueMappings() {
 
 ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI)
     : ARMGenRegisterBankInfo() {
+  static bool AlreadyInit = false;
   // We have only one set of register banks, whatever the subtarget
   // is. Therefore, the initialization of the RegBanks table should be
   // done only once. Indeed the table of all register banks
   // (ARM::RegBanks) is unique in the compiler. At some point, it
   // will get tablegen'ed and the whole constructor becomes empty.
-  static llvm::once_flag InitializeRegisterBankFlag;
+  if (AlreadyInit)
+    return;
+  AlreadyInit = true;
 
-  static auto InitializeRegisterBankOnce = [this](const auto &TRI) {
-    const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);
-    (void)RBGPR;
-    assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");
+  const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);
+  (void)RBGPR;
+  assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");
 
-    // Initialize the GPR bank.
-    assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&
-           "Subclass not added?");
-    assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&
-           "Subclass not added?");
-    assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&
-           "Subclass not added?");
-    assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) &&
-           "Subclass not added?");
-    assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) &&
-           "Subclass not added?");
-    assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) &&
-           "Subclass not added?");
-    assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) &&
-           "Subclass not added?");
-    assert(RBGPR.covers(
-               *TRI.getRegClass(ARM::tGPREven_and_tGPR_and_tcGPRRegClassID)) &&
-           "Subclass not added?");
-    assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) &&
-           "Subclass not added?");
-    assert(RBGPR.getSize() == 32 && "GPRs should hold up to 32-bit");
+  // Initialize the GPR bank.
+  assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&
+         "Subclass not added?");
+  assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&
+         "Subclass not added?");
+  assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&
+         "Subclass not added?");
+  assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) &&
+         "Subclass not added?");
+  assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) &&
+         "Subclass not added?");
+  assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) &&
+         "Subclass not added?");
+  assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) &&
+         "Subclass not added?");
+  assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPREven_and_tGPR_and_tcGPRRegClassID)) &&
+         "Subclass not added?");
+  assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) &&
+         "Subclass not added?");
+  assert(RBGPR.getSize() == 32 && "GPRs should hold up to 32-bit");
 
 #ifndef NDEBUG
-    ARM::checkPartialMappings();
-    ARM::checkValueMappings();
+  ARM::checkPartialMappings();
+  ARM::checkValueMappings();
 #endif
-  };
-
-  llvm::call_once(InitializeRegisterBankFlag, InitializeRegisterBankOnce, TRI);
 }
 
 const RegisterBank &