[PATCH] D73644: [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores.

[Mirko Brkusanin via Phabricator via llvm-commits]

mbrkusanin added a comment.

A few notes/questions:

1. Generated code was tested with Qemu:
  - For mips32r5 Qemu provides p5600
  - For mips64r6 Qemu provides i6400
  - For mips64r5 there is no cpu on Qemu with MSA and it appears that there won't be any hardware with Mips64r5 and MSA.
  - For mips32r6 Qemu only provides a cpu called mips32r6-generic which does not support MSA. I tested the code for this on mips64r6.

2. Names of the new intrinsics can be explained in the following way:

`__builtin_msa_ldr_d` (load right half)
`__builtin_msa_ldrq_w` (load right quarter)
`__builtin_msa_str_d` (store right half)
`__builtin_msa_strq_w` (store quarter)
Other proposed names are: ld1_d/ld1_w/st1_d/st1_w and ldc1/lwc1/sdc1/swc1. I have no strong preference and would not mind changing then if someone thinks they would fit better.

3. I did not make any tests for Clang (c/c++ test) since there are no tests for other intrinsics. Also should these new intrinsics be documented somewhere? Most other are corresponding to some instruction that already exists but these are actually pseudos.

4. emitLDRQ_W() and emitLDR_D() could be combined into one function but it decreases readability. Same with emitting stores: emitSTRQ_W() and emitSTR_D(). I already tried this and have the code ready if this would be more preferable.


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D73644