[PATCH] D73616: [ARM][LowOverheadLoops] Ensure memory predication
Sam Parker via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 29 03:16:22 PST 2020
samparker created this revision.
samparker added reviewers: dmgreen, SjoerdMeijer.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: LLVM.
While validating each MVE instruction, check that all instructions that touch memory are somehow predicated upon the VCTP.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D73616
Files:
llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D73616.241090.patch
Type: text/x-patch
Size: 19746 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200129/a817f0bd/attachment.bin>
More information about the llvm-commits
mailing list