[PATCH] D73283: Handle complex DWARF expressions in combination with "complex" registers

Tue Jan 28 08:30:48 PST 2020

dstenb added inline comments.

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Comment at: llvm/test/DebugInfo/MIR/ARM/subregister-complex-expression.mir:11
+#                    Q8 = {D16,               D17}
+# CHECK-NEXT:  DW_OP_bregx D16+0, DW_OP_bregx D17+0, DW_OP_constu 0x40, DW_OP_shl, DW_OP_or, DW_OP_constu 0x20, DW_OP_shr
+# CHECK-NOT: DW_TAG
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I don't have much knowledge about AArch64 so I might be overlooking something here, but I wonder if this expression really is valid, given the size of an element on the DWARF expression stack. The size of the elements on the stack is the size of an address on the target machine, which I assume is 64 bits on AArch64? DWARFv4 (and DWARFv5 for the generic type) specifies that the result of `DW_OP_shl` is truncated to fit in an element (modulo one plus the largest representable address), so it seems that the result of `(D17 << 64)` should be 0, and we'll just end up with the value of `(D16 >> 32)`?

Is this a case where we need to use DWARFv5's type operations (e.g. using `DW_OP_regval_type` to push the registers) to allow for the operations to be performed on a 128-bit base type?  

I think there in general are quite a lot of cases where LLVM needs to consider the size of the elements on the expression stack in which it currently doesn't.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73283/new/

https://reviews.llvm.org/D73283