[PATCH] D73483: [AMDGPU] fixed divergence driven shift operations selection

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

Is there a test for scalar selection?



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Comment at: llvm/lib/Target/AMDGPU/VOP2Instructions.td:548
 } // End SubtargetPredicate = isGFX6GFX7GFX10
+let SubtargetPredicate = isGFX6GFX7 in {
+defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, srl>;
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Any tests for GFX10 on this?


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Comment at: llvm/lib/Target/AMDGPU/VOP3Instructions.td:388
 let SchedRW = [Write64Bit] in {
-let SubtargetPredicate = isGFX6GFX7GFX10 in {
+let SubtargetPredicate = isGFX6GFX7 in {
 def V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>, shl>;
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Any tests for GFX10 on this?


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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir:2
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX6 %s
 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX6 %s
 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
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Ugh... Fiji is GFX8. Instead of dropping test for tahiti just fix the check-prefix for fiji.


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  https://reviews.llvm.org/D73483/new/

https://reviews.llvm.org/D73483