[PATCH] D73288: [InstCombine] Move negation handling into freelyNegateValue()

Nikita Popov via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jan 27 10:18:49 PST 2020


nikic marked an inline comment as done.
nikic added inline comments.


================
Comment at: llvm/lib/Transforms/InstCombine/InstructionCombining.cpp:867
+  unsigned BitWidth = V->getType()->getScalarSizeInBits();
+  if (match(V, m_ZExt(m_Value(A)))) {
+    // 0-(zext i1 A)  =>  sext i1 A
----------------
spatel wrote:
> Seems like this would be more efficient as a "switch(V->getOpcode())"? 
> 
> Then, we could combine cases like ashr/lshr by using Builder.CreateBinOp(V->getOpcode()...). Similarly combine zext/sext with Builder.CreateCast().
I've switched this to use switch, but ended up not combining the cases. The problem is that we need to swap the signedness of the opcodes (zext <-> sext, lshr <-> ashr), which is just awkward enough that keeping the cases separate looks more readable. (Especially as there is no direct API for creating an "lshr or ashr" with exact flag.)


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73288/new/

https://reviews.llvm.org/D73288





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