[llvm] d309b4e - AMDGPU/GlobalISel: Add baseline tests for fma/fmad selection
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 27 09:03:11 PST 2020
Author: Matt Arsenault
Date: 2020-01-27T09:02:13-08:00
New Revision: d309b4ebe471ecd30c71be5c7839b501d8c7e9b0
URL: https://github.com/llvm/llvm-project/commit/d309b4ebe471ecd30c71be5c7839b501d8c7e9b0
DIFF: https://github.com/llvm/llvm-project/commit/d309b4ebe471ecd30c71be5c7839b501d8c7e9b0.diff
LOG: AMDGPU/GlobalISel: Add baseline tests for fma/fmad selection
Added:
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir
new file mode 100644
index 000000000000..ec3f4449f60a
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir
@@ -0,0 +1,238 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -march=amdgcn -mcpu=gfx906 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9-DL %s
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
+
+---
+
+name: fma_f32
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2
+
+ ; GFX6-LABEL: name: fma_f32
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]]
+ ; GFX9-DL-LABEL: name: fma_f32
+ ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX9-DL: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
+ ; GFX9-DL: S_ENDPGM 0, implicit [[V_FMA_F32_]]
+ ; GFX10-LABEL: name: fma_f32
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX10: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_FMA_F32_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = COPY $vgpr2
+ %3:vgpr(s32) = G_FMA %0, %1, %2
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+
+name: fma_f32_fneg_src0
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2
+
+ ; GFX6-LABEL: name: fma_f32_fneg_src0
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]]
+ ; GFX9-DL-LABEL: name: fma_f32_fneg_src0
+ ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX9-DL: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
+ ; GFX9-DL: S_ENDPGM 0, implicit [[V_FMA_F32_]]
+ ; GFX10-LABEL: name: fma_f32_fneg_src0
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX10: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_FMA_F32_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = COPY $vgpr2
+ %3:vgpr(s32) = G_FNEG %0
+ %4:vgpr(s32) = G_FMA %3, %1, %2
+ S_ENDPGM 0, implicit %4
+
+...
+
+---
+
+name: fma_f32_fneg_src1
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2
+
+ ; GFX6-LABEL: name: fma_f32_fneg_src1
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]]
+ ; GFX9-DL-LABEL: name: fma_f32_fneg_src1
+ ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX9-DL: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
+ ; GFX9-DL: S_ENDPGM 0, implicit [[V_FMA_F32_]]
+ ; GFX10-LABEL: name: fma_f32_fneg_src1
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX10: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_FMA_F32_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = COPY $vgpr2
+ %3:vgpr(s32) = G_FNEG %1
+ %4:vgpr(s32) = G_FMA %0, %3, %2
+ S_ENDPGM 0, implicit %4
+
+...
+
+---
+
+name: fma_f32_fneg_src2
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2
+
+ ; GFX6-LABEL: name: fma_f32_fneg_src2
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]]
+ ; GFX9-DL-LABEL: name: fma_f32_fneg_src2
+ ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX9-DL: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec
+ ; GFX9-DL: S_ENDPGM 0, implicit [[V_FMA_F32_]]
+ ; GFX10-LABEL: name: fma_f32_fneg_src2
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX10: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_FMA_F32_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = COPY $vgpr2
+ %3:vgpr(s32) = G_FNEG %2
+ %4:vgpr(s32) = G_FMA %0, %1, %3
+ S_ENDPGM 0, implicit %4
+
+...
+
+---
+
+name: fma_f32_fabs_src2
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2
+
+ ; GFX6-LABEL: name: fma_f32_fabs_src2
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 2, [[COPY2]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]]
+ ; GFX9-DL-LABEL: name: fma_f32_fabs_src2
+ ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX9-DL: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 2, [[COPY2]], 0, 0, implicit $exec
+ ; GFX9-DL: S_ENDPGM 0, implicit [[V_FMA_F32_]]
+ ; GFX10-LABEL: name: fma_f32_fabs_src2
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX10: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 2, [[COPY2]], 0, 0, implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_FMA_F32_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = COPY $vgpr2
+ %3:vgpr(s32) = G_FABS %2
+ %4:vgpr(s32) = G_FMA %0, %1, %3
+ S_ENDPGM 0, implicit %4
+
+...
+
+---
+
+name: fma_f32_copy_fneg_src2
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2
+
+ ; GFX6-LABEL: name: fma_f32_copy_fneg_src2
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
+ ; GFX6: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY2]], implicit $exec
+ ; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 0, [[V_XOR_B32_e32_]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]]
+ ; GFX9-DL-LABEL: name: fma_f32_copy_fneg_src2
+ ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX9-DL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
+ ; GFX9-DL: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY2]], implicit $exec
+ ; GFX9-DL: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 0, [[V_XOR_B32_e32_]], 0, 0, implicit $exec
+ ; GFX9-DL: S_ENDPGM 0, implicit [[V_FMA_F32_]]
+ ; GFX10-LABEL: name: fma_f32_copy_fneg_src2
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
+ ; GFX10: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY2]], implicit $exec
+ ; GFX10: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 0, [[V_XOR_B32_e32_]], 0, 0, implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_FMA_F32_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = COPY $vgpr2
+ %3:vgpr(s32) = G_FNEG %2
+ %4:vgpr(s32) = COPY %3
+ %5:vgpr(s32) = G_FMA %0, %1, %4
+ S_ENDPGM 0, implicit %5
+
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir
new file mode 100644
index 000000000000..fde4fba9c282
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir
@@ -0,0 +1,199 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
+
+---
+
+name: fmad_f32
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2
+
+ ; GFX6-LABEL: name: fmad_f32
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX6: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_MAD_F32_]]
+ ; GFX10-LABEL: name: fmad_f32
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX10: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_MAD_F32_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = COPY $vgpr2
+ %3:vgpr(s32) = G_FMAD %0, %1, %2
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+
+name: fmad_f32_fneg_src0
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2
+
+ ; GFX6-LABEL: name: fmad_f32_fneg_src0
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX6: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_MAD_F32_]]
+ ; GFX10-LABEL: name: fmad_f32_fneg_src0
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX10: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_MAD_F32_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = COPY $vgpr2
+ %3:vgpr(s32) = G_FNEG %0
+ %4:vgpr(s32) = G_FMAD %3, %1, %2
+ S_ENDPGM 0, implicit %4
+
+...
+
+---
+
+name: fmad_f32_fneg_src1
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2
+
+ ; GFX6-LABEL: name: fmad_f32_fneg_src1
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX6: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_MAD_F32_]]
+ ; GFX10-LABEL: name: fmad_f32_fneg_src1
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX10: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_MAD_F32_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = COPY $vgpr2
+ %3:vgpr(s32) = G_FNEG %1
+ %4:vgpr(s32) = G_FMAD %0, %3, %2
+ S_ENDPGM 0, implicit %4
+
+...
+
+---
+
+name: fmad_f32_fneg_src2
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2
+
+ ; GFX6-LABEL: name: fmad_f32_fneg_src2
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX6: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_MAD_F32_]]
+ ; GFX10-LABEL: name: fmad_f32_fneg_src2
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX10: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_MAD_F32_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = COPY $vgpr2
+ %3:vgpr(s32) = G_FNEG %2
+ %4:vgpr(s32) = G_FMAD %0, %1, %3
+ S_ENDPGM 0, implicit %4
+
+...
+
+---
+
+name: fmad_f32_fabs_src2
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2
+
+ ; GFX6-LABEL: name: fmad_f32_fabs_src2
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX6: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 2, [[COPY2]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_MAD_F32_]]
+ ; GFX10-LABEL: name: fmad_f32_fabs_src2
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX10: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 2, [[COPY2]], 0, 0, implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_MAD_F32_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = COPY $vgpr2
+ %3:vgpr(s32) = G_FABS %2
+ %4:vgpr(s32) = G_FMAD %0, %1, %3
+ S_ENDPGM 0, implicit %4
+
+...
+
+---
+
+name: fmad_f32_copy_fneg_src2
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2
+
+ ; GFX6-LABEL: name: fmad_f32_copy_fneg_src2
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
+ ; GFX6: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY2]], implicit $exec
+ ; GFX6: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 0, [[V_XOR_B32_e32_]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_MAD_F32_]]
+ ; GFX10-LABEL: name: fmad_f32_copy_fneg_src2
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
+ ; GFX10: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY2]], implicit $exec
+ ; GFX10: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 0, [[V_XOR_B32_e32_]], 0, 0, implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_MAD_F32_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = COPY $vgpr2
+ %3:vgpr(s32) = G_FNEG %2
+ %4:vgpr(s32) = COPY %3
+ %5:vgpr(s32) = G_FMAD %0, %1, %4
+ S_ENDPGM 0, implicit %5
+
+...
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