[PATCH] D73454: [AMDGPU] Handle frame index base operands in memOpsHaveSameBasePtr

[Jay Foad via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGfcf5254fa792: [AMDGPU] Handle frame index base operands in memOpsHaveSameBasePtr (authored by foad).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73454/new/

https://reviews.llvm.org/D73454

Files:
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp


Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -408,11 +408,6 @@
                                   const MachineOperand &BaseOp1,
                                   const MachineInstr &MI2,
                                   const MachineOperand &BaseOp2) {
-  // Support only base operands with base registers.
-  // Note: this could be extended to support FI operands.
-  if (!BaseOp1.isReg() || !BaseOp2.isReg())
-    return false;
-
   if (BaseOp1.isIdenticalTo(BaseOp2))
     return true;
 


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