[llvm] fcf5254 - [AMDGPU] Handle frame index base operands in memOpsHaveSameBasePtr

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2020-01-27T14:45:21Z
New Revision: fcf5254fa792353852a6a7604206dd4e93ad0f99

URL: https://github.com/llvm/llvm-project/commit/fcf5254fa792353852a6a7604206dd4e93ad0f99
DIFF: https://github.com/llvm/llvm-project/commit/fcf5254fa792353852a6a7604206dd4e93ad0f99.diff

LOG: [AMDGPU] Handle frame index base operands in memOpsHaveSameBasePtr

Summary:
This is in preparation for getMemOperandsWithOffset returning more base
operands.

Reviewers: arsenm, rampitec

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, arphaman, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73454

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index f18f06754a55..d13cb8bec206 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -408,11 +408,6 @@ static bool memOpsHaveSameBasePtr(const MachineInstr &MI1,
                                   const MachineOperand &BaseOp1,
                                   const MachineInstr &MI2,
                                   const MachineOperand &BaseOp2) {
-  // Support only base operands with base registers.
-  // Note: this could be extended to support FI operands.
-  if (!BaseOp1.isReg() || !BaseOp2.isReg())
-    return false;
-
   if (BaseOp1.isIdenticalTo(BaseOp2))
     return true;