[llvm] f99ef54 - [InstCombine] Add extra shift(c1, add(c2, y)) tests for PR15141

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-01-26T19:04:12Z
New Revision: f99ef5455aad014eaf43278f59544619e558ecad

URL: https://github.com/llvm/llvm-project/commit/f99ef5455aad014eaf43278f59544619e558ecad
DIFF: https://github.com/llvm/llvm-project/commit/f99ef5455aad014eaf43278f59544619e558ecad.diff

LOG: [InstCombine] Add extra shift(c1,add(c2,y)) tests for PR15141

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/shift-add.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/shift-add.ll b/llvm/test/Transforms/InstCombine/shift-add.ll
index 497159f19b64..dd34233f7a47 100644
--- a/llvm/test/Transforms/InstCombine/shift-add.ll
+++ b/llvm/test/Transforms/InstCombine/shift-add.ll
@@ -5,7 +5,7 @@
 
 define i32 @shl_C1_add_A_C2_i32(i16 %A) {
 ; CHECK-LABEL: @shl_C1_add_A_C2_i32(
-; CHECK-NEXT:    [[B:%.*]] = zext i16 %A to i32
+; CHECK-NEXT:    [[B:%.*]] = zext i16 [[A:%.*]] to i32
 ; CHECK-NEXT:    [[D:%.*]] = shl i32 192, [[B]]
 ; CHECK-NEXT:    ret i32 [[D]]
 ;
@@ -27,7 +27,7 @@ define i32 @ashr_C1_add_A_C2_i32(i32 %A) {
 
 define i32 @lshr_C1_add_A_C2_i32(i32 %A) {
 ; CHECK-LABEL: @lshr_C1_add_A_C2_i32(
-; CHECK-NEXT:    [[B:%.*]] = and i32 %A, 65535
+; CHECK-NEXT:    [[B:%.*]] = and i32 [[A:%.*]], 65535
 ; CHECK-NEXT:    [[D:%.*]] = shl i32 192, [[B]]
 ; CHECK-NEXT:    ret i32 [[D]]
 ;
@@ -39,7 +39,7 @@ define i32 @lshr_C1_add_A_C2_i32(i32 %A) {
 
 define <4 x i32> @shl_C1_add_A_C2_v4i32(<4 x i16> %A) {
 ; CHECK-LABEL: @shl_C1_add_A_C2_v4i32(
-; CHECK-NEXT:    [[B:%.*]] = zext <4 x i16> %A to <4 x i32>
+; CHECK-NEXT:    [[B:%.*]] = zext <4 x i16> [[A:%.*]] to <4 x i32>
 ; CHECK-NEXT:    [[D:%.*]] = shl <4 x i32> <i32 6, i32 4, i32 undef, i32 -458752>, [[B]]
 ; CHECK-NEXT:    ret <4 x i32> [[D]]
 ;
@@ -51,7 +51,7 @@ define <4 x i32> @shl_C1_add_A_C2_v4i32(<4 x i16> %A) {
 
 define <4 x i32> @ashr_C1_add_A_C2_v4i32(<4 x i32> %A) {
 ; CHECK-LABEL: @ashr_C1_add_A_C2_v4i32(
-; CHECK-NEXT:    [[B:%.*]] = and <4 x i32> %A, <i32 0, i32 15, i32 255, i32 65535>
+; CHECK-NEXT:    [[B:%.*]] = and <4 x i32> [[A:%.*]], <i32 0, i32 15, i32 255, i32 65535>
 ; CHECK-NEXT:    [[D:%.*]] = ashr <4 x i32> <i32 6, i32 1, i32 undef, i32 -1>, [[B]]
 ; CHECK-NEXT:    ret <4 x i32> [[D]]
 ;
@@ -63,7 +63,7 @@ define <4 x i32> @ashr_C1_add_A_C2_v4i32(<4 x i32> %A) {
 
 define <4 x i32> @lshr_C1_add_A_C2_v4i32(<4 x i32> %A) {
 ; CHECK-LABEL: @lshr_C1_add_A_C2_v4i32(
-; CHECK-NEXT:    [[B:%.*]] = and <4 x i32> %A, <i32 0, i32 15, i32 255, i32 65535>
+; CHECK-NEXT:    [[B:%.*]] = and <4 x i32> [[A:%.*]], <i32 0, i32 15, i32 255, i32 65535>
 ; CHECK-NEXT:    [[D:%.*]] = lshr <4 x i32> <i32 6, i32 1, i32 undef, i32 65535>, [[B]]
 ; CHECK-NEXT:    ret <4 x i32> [[D]]
 ;
@@ -72,3 +72,54 @@ define <4 x i32> @lshr_C1_add_A_C2_v4i32(<4 x i32> %A) {
   %D = lshr <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %C
   ret <4 x i32> %D
 }
+
+define <4 x i32> @shl_C1_add_A_C2_v4i32_splat(i16 %I) {
+; CHECK-LABEL: @shl_C1_add_A_C2_v4i32_splat(
+; CHECK-NEXT:    [[A:%.*]] = zext i16 [[I:%.*]] to i32
+; CHECK-NEXT:    [[B:%.*]] = insertelement <4 x i32> undef, i32 [[A]], i32 0
+; CHECK-NEXT:    [[C:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[D:%.*]] = add <4 x i32> [[C]], <i32 0, i32 1, i32 50, i32 16>
+; CHECK-NEXT:    [[E:%.*]] = shl <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, [[D]]
+; CHECK-NEXT:    ret <4 x i32> [[E]]
+;
+  %A = zext i16 %I to i32
+  %B = insertelement <4 x i32> undef, i32 %A, i32 0
+  %C = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
+  %D = add <4 x i32> %C, <i32 0, i32 1, i32 50, i32 16>
+  %E = shl <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %D
+  ret <4 x i32> %E
+}
+
+define <4 x i32> @ashr_C1_add_A_C2_v4i32_splat(i16 %I) {
+; CHECK-LABEL: @ashr_C1_add_A_C2_v4i32_splat(
+; CHECK-NEXT:    [[A:%.*]] = zext i16 [[I:%.*]] to i32
+; CHECK-NEXT:    [[B:%.*]] = insertelement <4 x i32> undef, i32 [[A]], i32 0
+; CHECK-NEXT:    [[C:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[D:%.*]] = add <4 x i32> [[C]], <i32 0, i32 1, i32 50, i32 16>
+; CHECK-NEXT:    [[E:%.*]] = ashr <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, [[D]]
+; CHECK-NEXT:    ret <4 x i32> [[E]]
+;
+  %A = zext i16 %I to i32
+  %B = insertelement <4 x i32> undef, i32 %A, i32 0
+  %C = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
+  %D = add <4 x i32> %C, <i32 0, i32 1, i32 50, i32 16>
+  %E = ashr <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %D
+  ret <4 x i32> %E
+}
+
+define <4 x i32> @lshr_C1_add_A_C2_v4i32_splat(i16 %I) {
+; CHECK-LABEL: @lshr_C1_add_A_C2_v4i32_splat(
+; CHECK-NEXT:    [[A:%.*]] = zext i16 [[I:%.*]] to i32
+; CHECK-NEXT:    [[B:%.*]] = insertelement <4 x i32> undef, i32 [[A]], i32 0
+; CHECK-NEXT:    [[C:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[D:%.*]] = add <4 x i32> [[C]], <i32 0, i32 1, i32 50, i32 16>
+; CHECK-NEXT:    [[E:%.*]] = lshr <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, [[D]]
+; CHECK-NEXT:    ret <4 x i32> [[E]]
+;
+  %A = zext i16 %I to i32
+  %B = insertelement <4 x i32> undef, i32 %A, i32 0
+  %C = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
+  %D = add <4 x i32> %C, <i32 0, i32 1, i32 50, i32 16>
+  %E = lshr <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %D
+  ret <4 x i32> %E
+}