[llvm] 9fa0f23 - [PATCH] [Target] Test commit

Evandro Menezes via llvm-commits llvm-commits at lists.llvm.org
Fri Jan 24 13:58:57 PST 2020


Author: Evandro Menezes
Date: 2020-01-24T15:56:08-06:00
New Revision: 9fa0f236d5011630932e8358e45f81cd21861911

URL: https://github.com/llvm/llvm-project/commit/9fa0f236d5011630932e8358e45f81cd21861911
DIFF: https://github.com/llvm/llvm-project/commit/9fa0f236d5011630932e8358e45f81cd21861911.diff

LOG: [PATCH] [Target] Test commit

Modify comment to reflect the current users of `Regisgter.CostPerUse`.

Added: 
    

Modified: 
    llvm/include/llvm/Target/Target.td

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index cdc9b640e74e..eda08bb28d4c 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -166,8 +166,9 @@ class Register<string n, list<string> altNames = []> {
   // CostPerUse - Additional cost of instructions using this register compared
   // to other registers in its class. The register allocator will try to
   // minimize the number of instructions using a register with a CostPerUse.
-  // This is used by the x86-64 and ARM Thumb targets where some registers
-  // require larger instruction encodings.
+  // This is used by the ARC target, by the ARM Thumb and x86-64 targets, where
+  // some registers require larger instruction encodings, by the RISC-V target,
+  // where some registers preclude using some C instructions.
   int CostPerUse = 0;
 
   // CoveredBySubRegs - When this bit is set, the value of this register is


        


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