[PATCH] D73276: [VE] aligned load/store isel patterns

[Simon Moll via Phabricator via llvm-commits]

simoll planned changes to this revision.
simoll marked an inline comment as done.
simoll added inline comments.


================
Comment at: llvm/lib/Target/VE/VEISelDAGToDAG.cpp:72
+  if (CurDAG->isBaseWithConstantOffset(Addr)) {
+    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
+      if (isInt<13>(CN->getSExtValue())) {
----------------
Will be replaced with a `cast`.. we know that the operand is a constant.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73276/new/

https://reviews.llvm.org/D73276