[PATCH] D73341: [GlobalISel] Use pointer type size for offset constant when lowering load/stores

Dominik Montada via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Jan 24 03:01:08 PST 2020


gargaroff created this revision.
gargaroff added reviewers: dsanders, arsenm.
Herald added subscribers: llvm-commits, Petar.Avramovic, volkan, hiraditya, rovka, wdng.
Herald added a project: LLVM.

Lowering non-power-of-2 G_LOAD/G_STORE introduces a G_PTR_ADD. The offset constant used by this instruction uses 64-bit unconditionally. This causes legalization to fail for backends that don't use 64-bit pointers.

This patch uses the size of the pointer type for the type of the offset constant to fix this problem.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D73341

Files:
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp


Index: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -2224,8 +2224,8 @@
         auto LargeLoad =
             MIRBuilder.buildLoad(LargeLdReg, PtrReg, *LargeMMO);
 
-        auto OffsetCst =
-            MIRBuilder.buildConstant(LLT::scalar(64), LargeSplitSize / 8);
+        auto OffsetCst = MIRBuilder.buildConstant(
+            LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8);
         Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy);
         auto SmallPtr =
             MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0));


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