[PATCH] D73338: [AMDGPU] Fix GCN regpressure trackers for INLINEASM instructions

[Valery Pykhtin via Phabricator via llvm-commits]

vpykhtin created this revision.
vpykhtin added reviewers: rampitec, arsenm.
Herald added subscribers: llvm-commits, kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.

Replace iteration over defs() with operands() as INLINEASM instruction isn't compatible with defs() - it has completly different order of operands: asm string, flags and pairs of flags:operand. defs() assumes all def operands go sequentally from the beginning of operands.

How LLVM could work all these years? Should an assert not using on INLINEASM in defs be added?

Not sure how to test this.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D73338

Files:
  llvm/lib/Target/AMDGPU/GCNRegPressure.cpp


Index: llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
+++ llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
@@ -327,8 +327,9 @@
   // update max pressure
   MaxPressure = max(AtMIPressure, MaxPressure);
 
-  for (const auto &MO : MI.defs()) {
-    if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()) || MO.isDead())
+  for (const auto &MO : MI.operands()) {
+    if (!MO.isReg() || !MO.isDef() ||
+        !Register::isVirtualRegister(MO.getReg()) || MO.isDead())
       continue;
 
     auto Reg = MO.getReg();
@@ -403,8 +404,8 @@
   LastTrackedMI = &*NextMI++;
 
   // Add new registers or mask bits.
-  for (const auto &MO : LastTrackedMI->defs()) {
-    if (!MO.isReg())
+  for (const auto &MO : LastTrackedMI->operands()) {
+    if (!MO.isReg() || !MO.isDef())
       continue;
     Register Reg = MO.getReg();
     if (!Register::isVirtualRegister(Reg))


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