[llvm] 4d14772 - AMDGPU/GlobalISel: Remove redundant or patterns

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2020-01-22T21:45:51-05:00
New Revision: 4d14772f5c2938b8a266d626a73fd7c7cf3ebba5

URL: https://github.com/llvm/llvm-project/commit/4d14772f5c2938b8a266d626a73fd7c7cf3ebba5
DIFF: https://github.com/llvm/llvm-project/commit/4d14772f5c2938b8a266d626a73fd7c7cf3ebba5.diff

LOG: AMDGPU/GlobalISel: Remove redundant or patterns

These ended up with higher priority than or3 patterns in a future
patch. This also fixes the using VOP2 forms.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUGISel.td
    llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
index 1a8134788f8c..44b27dde14cc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
@@ -202,9 +202,6 @@ multiclass GISelVop2IntrPat <
   def : GISelVop2CommutePat <node, inst, dst_vt, src_vt>;
 }
 
-def : GISelSop2Pat <or, S_OR_B32, i32>;
-def : GISelVop2Pat <or, V_OR_B32_e32, i32>;
-
 // Since GlobalISel is more flexible then SelectionDAG, I think we can get
 // away with adding patterns for integer types and not legalizing all
 // loads and stores to vector types.  This should help simplify the load/store

diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
index 444767ab206d..33a956a04be2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
@@ -301,8 +301,8 @@ body: |
     ; WAVE32: $vcc_hi = IMPLICIT_DEF
     ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-    ; WAVE32: [[V_OR_B32_e32_:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[COPY]], [[COPY1]], implicit $exec
-    ; WAVE32: S_ENDPGM 0, implicit [[V_OR_B32_e32_]]
+    ; WAVE32: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
+    ; WAVE32: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s32) = COPY $vgpr1
     %2:vgpr(s32) = G_OR %0, %1