[llvm] fb8a3d1 - Regenerate test/CodeGen/ARM/vext.ll. NFC.

[Stanislav Mekhanoshin via llvm-commits]

Author: Stanislav Mekhanoshin
Date: 2020-01-22T08:56:08-08:00
New Revision: fb8a3d18340e0b5c2266a84d6a5158f5cd8bc9a2

URL: https://github.com/llvm/llvm-project/commit/fb8a3d18340e0b5c2266a84d6a5158f5cd8bc9a2
DIFF: https://github.com/llvm/llvm-project/commit/fb8a3d18340e0b5c2266a84d6a5158f5cd8bc9a2.diff

LOG: Regenerate test/CodeGen/ARM/vext.ll. NFC.

This is to pre-commit whitespace only changes before D73132.

Added: 
    

Modified: 
    llvm/test/CodeGen/ARM/vext.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/ARM/vext.ll b/llvm/test/CodeGen/ARM/vext.ll
index 397680c5b0cf..c00bc41c25d5 100644
--- a/llvm/test/CodeGen/ARM/vext.ll
+++ b/llvm/test/CodeGen/ARM/vext.ll
@@ -199,10 +199,10 @@ define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ; CHECK-LABEL: test_undef:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vldr  d16, [r1]
-; CHECK-NEXT:    vldr  d17, [r0, #8]
+; CHECK-NEXT:    vldr d16, [r1]
+; CHECK-NEXT:    vldr d17, [r0, #8]
 ; CHECK-NEXT:    vzip.16 d17, d16
-; CHECK-NEXT:    vmov  r0, r1, d17
+; CHECK-NEXT:    vmov r0, r1, d17
 ; CHECK-NEXT:    mov pc, lr
         %tmp1 = load <8 x i16>, <8 x i16>* %A
         %tmp2 = load <8 x i16>, <8 x i16>* %B
@@ -259,24 +259,24 @@ define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind {
 define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ; CHECK-LABEL: test_illegal:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:	vld1.64	{d16, d17}, [r0]
-; CHECK-NEXT:	vorr	d22, d16, d16
-; CHECK-NEXT:	vmov.u16	r0, d16[0]
-; CHECK-NEXT:	vorr	d23, d16, d16
-; CHECK-NEXT:	vmov.u16	r2, d17[3]
-; CHECK-NEXT:	vmov.u16	r3, d17[1]
-; CHECK-NEXT:	vld1.64	{d18, d19}, [r1]
-; CHECK-NEXT:	vmov.u16	r1, d19[1]
-; CHECK-NEXT:	vuzp.16	d22, d23
-; CHECK-NEXT:	vuzp.16	d22, d18
-; CHECK-NEXT:	vmov.16	d20[0], r0
-; CHECK-NEXT:	vmov.16	d20[1], r2
-; CHECK-NEXT:	vmov.16	d20[2], r3
-; CHECK-NEXT:	vmov.16	d20[3], r1
-; CHECK-NEXT:	vext.16	d21, d16, d18, #3
-; CHECK-NEXT:	vmov	r0, r1, d20
-; CHECK-NEXT:	vmov	r2, r3, d21
-; CHECK-NEXT:	mov	pc, lr
+; CHECK-NEXT:    vld1.64 {d16, d17}, [r0]
+; CHECK-NEXT:    vorr d22, d16, d16
+; CHECK-NEXT:    vmov.u16 r0, d16[0]
+; CHECK-NEXT:    vorr d23, d16, d16
+; CHECK-NEXT:    vmov.u16 r2, d17[3]
+; CHECK-NEXT:    vmov.u16 r3, d17[1]
+; CHECK-NEXT:    vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT:    vmov.u16 r1, d19[1]
+; CHECK-NEXT:    vuzp.16 d22, d23
+; CHECK-NEXT:    vuzp.16 d22, d18
+; CHECK-NEXT:    vmov.16 d20[0], r0
+; CHECK-NEXT:    vmov.16 d20[1], r2
+; CHECK-NEXT:    vmov.16 d20[2], r3
+; CHECK-NEXT:    vmov.16 d20[3], r1
+; CHECK-NEXT:    vext.16 d21, d16, d18, #3
+; CHECK-NEXT:    vmov r0, r1, d20
+; CHECK-NEXT:    vmov r2, r3, d21
+; CHECK-NEXT:    mov pc, lr
        %tmp1 = load <8 x i16>, <8 x i16>* %A
        %tmp2 = load <8 x i16>, <8 x i16>* %B
        %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 7, i32 5, i32 13, i32 3, i32 2, i32 2, i32 9>