[llvm] 0bf434c - AMDGPU: Fix element size assertion

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2020-01-22T11:18:45-05:00
New Revision: 0bf434ccd5627c385af96ef7a456294f195cca43

URL: https://github.com/llvm/llvm-project/commit/0bf434ccd5627c385af96ef7a456294f195cca43
DIFF: https://github.com/llvm/llvm-project/commit/0bf434ccd5627c385af96ef7a456294f195cca43.diff

LOG: AMDGPU: Fix element size assertion

The GlobalISel usage called this with bits, but the DAG usage was
incorrectly using bytes.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 0a8f188bc18c..2f7f75530bb6 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -3505,7 +3505,7 @@ static MachineBasicBlock *emitIndirectDst(MachineInstr &MI,
   }
 
   const MCInstrDesc &MovRelDesc
-    = TII->getIndirectRegWritePseudo(TRI.getRegSizeInBits(*VecRC), 4, false);
+    = TII->getIndirectRegWritePseudo(TRI.getRegSizeInBits(*VecRC), 32, false);
 
   if (setM0ToIndexFromSGPR(TII, MRI, MI, Offset, UseGPRIdxMode, false)) {
     MachineBasicBlock::iterator I(&MI);