[PATCH] D72964: AMDGPU: Fix interaction of tfe and d16

[Nicolai Hähnle via Phabricator via llvm-commits]

nhaehnle accepted this revision.
nhaehnle added a comment.
This revision is now accepted and ready to land.

One question, but apart from that LGTM.

The register initialization code is suboptimal, bit I'm going to write up a patch for that.



================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:5311
 
-  // Extract the TexFail result and insert into aggregate return
-  SmallVector<SDValue, 1> TFCElt;
-  DAG.ExtractVectorElements(N, TFCElt, DMaskPop, 1);
-  SDValue TFCRes = DAG.getNode(ISD::BITCAST, DL, ResultTypes[1], TFCElt[0]);
-  return DAG.getMergeValues({PreTFCRes, TFCRes, SDValue(Result, 1)}, DL);
+  return DAG.getMergeValues({Data, SDValue(Result, 1)}, DL);
 }
----------------
When does this case actually happen?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72964/new/

https://reviews.llvm.org/D72964