[PATCH] D73170: Handle subregs and superregs in callee-saved register mask

[James Clarke via Phabricator via llvm-commits]

jrtc27 created this revision.
jrtc27 added reviewers: joerg, hfinkel, nemanjai, jhibbits.
Herald added subscribers: llvm-commits, luismarques, steven.zhang, s.egerton, lenary, jsji, PkmX, simoncook, hiraditya, arichardson.
Herald added a project: LLVM.

If a target lists both a subreg and a superreg in a callee-saved
register mask, the prolog will spill both aliasing registers. Instead,
don't spill the subreg if a superreg is being spilled. This case is hit by the
PowerPC SPE code, as well as a modified RISC-V backend for CHERI I maintain out
of tree.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D73170

Files:
  llvm/lib/CodeGen/PrologEpilogInserter.cpp
  llvm/test/CodeGen/PowerPC/spe.ll

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