[PATCH] D72961: [AArch64] Don't generate gpr CSEL instructions in early-ifcvt if regclasses aren't compatible.

[Amara Emerson via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG67a87753225e: [AArch64] Don't generate gpr CSEL instructions in early-ifcvt if regclasses… (authored by aemerson).

Changed prior to commit:
  https://reviews.llvm.org/D72961?vs=239350&id=239461#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72961/new/

https://reviews.llvm.org/D72961

Files:
  llvm/include/llvm/CodeGen/TargetInstrInfo.h
  llvm/lib/CodeGen/EarlyIfConversion.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.h
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.h
  llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
  llvm/lib/Target/SystemZ/SystemZInstrInfo.h
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86InstrInfo.h
  llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir

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