[PATCH] D73135: [AArch64][ARM] Always expand ordered vector reductions (PR44600)

Tue Jan 21 13:00:56 PST 2020

nikic created this revision.
nikic added reviewers: sdesmalen, aemerson, efriedma.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls.
Herald added a project: LLVM.

fadd/fmul reductions without reassoc are lowered to VECREDUCE_STRICT_FADD/FMUL nodes, which currently have zero legalization support. Until that is in place, force them to be expanded so we don't get legalization assertions.

This partially fixes https://bugs.llvm.org/show_bug.cgi?id=44600. The other part of the issue is fmax/fmin NaN handling on AArch64. This seems to be underspecified right now, as langref doesn't tell us which NaN semantics the reductions are supposed to use...

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D73135

Files:
  llvm/lib/CodeGen/ExpandReductions.cpp
  llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll

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