[PATCH] D72974: [mlir] Fix LLVM intrinsic convesion generator for overloadable types.

[River Riddle via Phabricator via llvm-commits]

rriddle accepted this revision.
rriddle added inline comments.
This revision is now accepted and ready to land.


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Comment at: mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp:34
 
+using IndicesTy = llvm::SmallVector<int, 4>;
+
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rriddle wrote:
> nit: Can you just use a SmallBitVector instead?
Please add a comment for this using directive.


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Comment at: mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp:167
+  auto overloadedOps = intr.getOverloadableOperandsIdxs();
+  auto overloadedRes = intr.getOverloadableResultsIdxs();
   os << "    llvm::Module *module = builder.GetInsertBlock()->getModule();\n";
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nit: Swap these two variables to match the loop order below.


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Comment at: mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp:180
+  }
+  if (!overloadedRes.empty() || !overloadedOps.empty())
+    os << "\n  ";
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These  !empty() checks need to be changed to 'any' now.


Repository:
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  https://reviews.llvm.org/D72974/new/

https://reviews.llvm.org/D72974