[PATCH] D73097: [AArch64][SVE] Add intrinsics for FFR manipulation

[Eli Friedman via Phabricator via llvm-commits]

efriedma accepted this revision.
efriedma added a comment.
This revision is now accepted and ready to land.

LGTM

I think it's fairly likely that we'll eventually decide that the correct model of the FFR register doesn't require these intrinsics at all.  They're just register copies, which is not something we normally model explicitly in IR. Instead, it would be much simpler to reason about the semantics if the faulting load intrinsics took the FFR value explicitly as an operand/result.  (clang can lower the ACLE intrinsics onto this model by storing "FFR" into a hidden alloca.)

In the meantime, though, this implementation looks correct, ignoring the issue with FFR getting clobbered we discussed before.

It would be nice if we could use COPY MachineInstrs instead of introducing new pseudo-instructions, but I guess that has the same issue of reading a register that wasn't previously defined.


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D73097