[PATCH] D73092: [VE] i<N> and fp32/64 arguments, return values and constants

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/VE/VEISelLowering.cpp:94
+    // in the high bits of the register.
+    if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
+      OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
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I think this bit is the most interesting part to test here, but I don't see a test for this


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Comment at: llvm/lib/Target/VE/VEInstrInfo.td:420-423
+def : Pat<(sext_inreg I32:$src, i1),
+          (SRAri (SLAri $src, 31), 31)>;
+def : Pat<(sext_inreg I64:$src, i1),
+          (SRAXri (SLLri $src, 63), 63)>;
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If you're just going to implement these with the shifts, you're probably better off making these expand instead for the combining value


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D73092/new/

https://reviews.llvm.org/D73092