[llvm] c72aa27 - AMDDGPU/GlobalISel: Fix RegBankSelect for llvm.amdgcn.ps.live

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2020-01-20T23:21:53-05:00
New Revision: c72aa27f917832af8a0d8d3a8aa9974411c30610

URL: https://github.com/llvm/llvm-project/commit/c72aa27f917832af8a0d8d3a8aa9974411c30610
DIFF: https://github.com/llvm/llvm-project/commit/c72aa27f917832af8a0d8d3a8aa9974411c30610.diff

LOG: AMDDGPU/GlobalISel: Fix RegBankSelect for llvm.amdgcn.ps.live

Added: 
    llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 000e904c1138..16ee9ecbf900 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -2996,6 +2996,10 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
         = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Size);
       break;
     }
+    case Intrinsic::amdgcn_ps_live: {
+      OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1);
+      break;
+    }
     case Intrinsic::amdgcn_s_buffer_load: {
       // FIXME: This should be moved to G_INTRINSIC_W_SIDE_EFFECTS
       Register RSrc = MI.getOperand(2).getReg();   // SGPR

diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
new file mode 100644
index 000000000000..33e3c6e6f870
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
@@ -0,0 +1,17 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: ps_live
+legalized: true
+
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: ps_live
+    ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.ps.live)
+    ; CHECK: S_ENDPGM 0, implicit [[INT]](s1)
+    %0:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.ps.live)
+    S_ENDPGM 0, implicit %0
+...
+