[PATCH] D70858: [GlobalISel][RFC] Importing insert/extract vector element patterns

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h:60-65
+  /// The operation should be implemented in terms of a wider scalar
+  /// base-type. Used for vector truncating insert or extending extract.
+  /// Changes opcode.
+  WidenVectorInsOrExtScalar,
+
   /// The (vector) operation should be implemented by splitting it into
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Why is a new legalize action needed? Why can't this just specify the existing action on the scalar operand?


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Comment at: llvm/utils/TableGen/CodeGenRegisters.cpp:1011-1014
+  // It's ok to have a few classes with same size as BiggestSuperRegRC.
+  assert(SuperRegRCs.front()->getMembers().size() ==
+             BiggestSuperRegRC->getMembers().size() &&
+         "Biggest class wasn't first");
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I have a different workaround for this in D72771


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Comment at: llvm/utils/TableGen/CodeGenRegisters.cpp:1057-1078
+
+        // Mips aliases same physical registers on a few diffent classes for
+        // vectors. They hold different vector types of same total size in bits.
+        // They all have same subclassess, and we want to return
+        // std::make_pair(BiggestSuperRegRC, fgr32)
+        if ((ChosenSuperRegClass->getMembers().size() ==
+             BiggestSuperRegRC->getMembers().size()) &&
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This all looks like more workaround for D72771. I think the mips register definitions should just be fixed to not have aliases


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Comment at: llvm/utils/TableGen/GlobalISelEmitter.cpp:2569
 
+class TempSubRegRenderer : public OperandRenderer {
+protected:
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I reproduced approximately the same thing in D72788


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  https://reviews.llvm.org/D70858/new/

https://reviews.llvm.org/D70858