[PATCH] D72934: [ARM,MVE] Support immediate vbicq,vorrq,vmvnq intrinsics.

Mon Jan 20 05:21:52 PST 2020

dmgreen added a comment.

What is the reason that this can't be lowered in tablegen, in the same way as the VMOVimm's are?

For vbic vs vmovlb, the vmovlb does include a free register move, so may under some circumstances be slightly better. Like you say, it's mostly benign, but may be worth updating the MVE_VMOVL patterns.

Do you have any tests for what would be invalid bic values under MVE?

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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:12181
       BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
     if (SplatBitSize <= 64) {
       EVT VbicVT;
----------------
This is OK because we are passing OtherModImm to isVMOVModifiedImm, and MVE supports the same patterns as NEON?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72934/new/

https://reviews.llvm.org/D72934