[PATCH] D73023: [DAG] Enable ISD::EXTRACT_SUBVECTOR SimplifyMultipleUseDemandedBits handling

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: efriedma, lebedev.ri, spatel, craig.topper.
Herald added a subscriber: hiraditya.
Herald added a project: LLVM.

This allows SimplifyDemandedBits to call SimplifyMultipleUseDemandedBits to create a simpler ISD::EXTRACT_SUBVECTOR, which is particularly useful for cases where we're splitting into subvectors anyhow.

@spatel I do have a concern that X86TargetLowering::shouldReduceLoadWidth is being a little too permissive in the pr31956.ll case - it results in multiple loads of a constant pool vector - any thoughts?


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D73023

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
  llvm/test/CodeGen/X86/avx-vperm2x128.ll
  llvm/test/CodeGen/X86/bitcast-setcc-256.ll
  llvm/test/CodeGen/X86/bitcast-vector-bool.ll
  llvm/test/CodeGen/X86/masked_load.ll
  llvm/test/CodeGen/X86/movmsk-cmp.ll
  llvm/test/CodeGen/X86/pr31956.ll
  llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll
  llvm/test/CodeGen/X86/vec_int_to_fp.ll

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