[llvm] d607572 - [ARM] MVE VLDn post inc tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 19 23:47:27 PST 2020
Author: David Green
Date: 2020-01-20T06:57:07Z
New Revision: d6075726b90184c2f3ff111991e92b21ee6b1475
URL: https://github.com/llvm/llvm-project/commit/d6075726b90184c2f3ff111991e92b21ee6b1475
DIFF: https://github.com/llvm/llvm-project/commit/d6075726b90184c2f3ff111991e92b21ee6b1475.diff
LOG: [ARM] MVE VLDn post inc tests. NFC
Added:
llvm/test/CodeGen/Thumb2/mve-vld2-post.ll
llvm/test/CodeGen/Thumb2/mve-vld4-post.ll
llvm/test/CodeGen/Thumb2/mve-vst2-post.ll
llvm/test/CodeGen/Thumb2/mve-vst4-post.ll
Modified:
llvm/test/CodeGen/Thumb2/mve-intrinsics/vld24.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/Thumb2/mve-intrinsics/vld24.ll b/llvm/test/CodeGen/Thumb2/mve-intrinsics/vld24.ll
index a8036a3ce3a9..5ad97fadc6d0 100644
--- a/llvm/test/CodeGen/Thumb2/mve-intrinsics/vld24.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-intrinsics/vld24.ll
@@ -21,6 +21,22 @@ entry:
ret %struct.float16x8x2_t %4
}
+define arm_aapcs_vfpcc half *@test_vld2q_f16_post(half* %addr, <8 x half>* %dst) {
+; CHECK-LABEL: test_vld2q_f16_post:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vld20.16 {q0, q1}, [r0]
+; CHECK-NEXT: vld21.16 {q0, q1}, [r0]
+; CHECK-NEXT: adds r0, #32
+; CHECK-NEXT: vstrw.32 q0, [r1]
+; CHECK-NEXT: bx lr
+entry:
+ %0 = tail call { <8 x half>, <8 x half> } @llvm.arm.mve.vld2q.v8f16.p0f16(half* %addr)
+ %1 = extractvalue { <8 x half>, <8 x half> } %0, 0
+ store <8 x half> %1, <8 x half> *%dst, align 4
+ %2 = getelementptr half, half *%addr, i32 16
+ ret half *%2
+}
+
declare { <8 x half>, <8 x half> } @llvm.arm.mve.vld2q.v8f16.p0f16(half*)
define arm_aapcs_vfpcc %struct.uint8x16x4_t @test_vld4q_u8(i8* %addr) {
@@ -44,6 +60,24 @@ entry:
ret %struct.uint8x16x4_t %8
}
+define arm_aapcs_vfpcc i8* @test_vld4q_u8_post(i8* %addr, <16 x i8>* %dst) {
+; CHECK-LABEL: test_vld4q_u8_post:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vld40.8 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: vld41.8 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: vld42.8 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: vld43.8 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: adds r0, #64
+; CHECK-NEXT: vstrw.32 q0, [r1]
+; CHECK-NEXT: bx lr
+entry:
+ %0 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.mve.vld4q.v16i8.p0i8(i8* %addr)
+ %1 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %0, 0
+ store <16 x i8> %1, <16 x i8> *%dst, align 4
+ %2 = getelementptr i8, i8 *%addr, i32 64
+ ret i8* %2
+}
+
declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.mve.vld4q.v16i8.p0i8(i8*)
define arm_aapcs_vfpcc void @test_vst2q_u32(i32* %addr, %struct.uint32x4x2_t %value.coerce) {
@@ -62,6 +96,24 @@ entry:
ret void
}
+define arm_aapcs_vfpcc i32* @test_vst2q_u32_post(i32* %addr, %struct.uint32x4x2_t %value.coerce) {
+; CHECK-LABEL: test_vst2q_u32_post:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: vst20.32 {q0, q1}, [r0]
+; CHECK-NEXT: vst21.32 {q0, q1}, [r0]
+; CHECK-NEXT: adds r0, #32
+; CHECK-NEXT: bx lr
+entry:
+ %value.coerce.fca.0.0.extract = extractvalue %struct.uint32x4x2_t %value.coerce, 0, 0
+ %value.coerce.fca.0.1.extract = extractvalue %struct.uint32x4x2_t %value.coerce, 0, 1
+ tail call void @llvm.arm.mve.vst2q.p0i32.v4i32(i32* %addr, <4 x i32> %value.coerce.fca.0.0.extract, <4 x i32> %value.coerce.fca.0.1.extract, i32 0)
+ tail call void @llvm.arm.mve.vst2q.p0i32.v4i32(i32* %addr, <4 x i32> %value.coerce.fca.0.0.extract, <4 x i32> %value.coerce.fca.0.1.extract, i32 1)
+ %g = getelementptr i32, i32 *%addr, i32 8
+ ret i32* %g
+}
+
declare void @llvm.arm.mve.vst2q.p0i32.v4i32(i32*, <4 x i32>, <4 x i32>, i32)
define arm_aapcs_vfpcc void @test_vst2q_f16(half* %addr, %struct.float16x8x2_t %value.coerce) {
@@ -80,6 +132,24 @@ entry:
ret void
}
+define arm_aapcs_vfpcc half* @test_vst2q_f16_post(half* %addr, %struct.float16x8x2_t %value.coerce) {
+; CHECK-LABEL: test_vst2q_f16_post:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: vst20.16 {q0, q1}, [r0]
+; CHECK-NEXT: vst21.16 {q0, q1}, [r0]
+; CHECK-NEXT: adds r0, #32
+; CHECK-NEXT: bx lr
+entry:
+ %value.coerce.fca.0.0.extract = extractvalue %struct.float16x8x2_t %value.coerce, 0, 0
+ %value.coerce.fca.0.1.extract = extractvalue %struct.float16x8x2_t %value.coerce, 0, 1
+ call void @llvm.arm.mve.vst2q.p0f16.v8f16(half* %addr, <8 x half> %value.coerce.fca.0.0.extract, <8 x half> %value.coerce.fca.0.1.extract, i32 0)
+ call void @llvm.arm.mve.vst2q.p0f16.v8f16(half* %addr, <8 x half> %value.coerce.fca.0.0.extract, <8 x half> %value.coerce.fca.0.1.extract, i32 1)
+ %g = getelementptr half, half *%addr, i32 16
+ ret half* %g
+}
+
declare void @llvm.arm.mve.vst2q.p0f16.v8f16(half*, <8 x half>, <8 x half>, i32)
define arm_aapcs_vfpcc void @test_vst4q_s8(i8* %addr, %struct.int8x16x4_t %value.coerce) {
@@ -106,4 +176,30 @@ entry:
ret void
}
+define arm_aapcs_vfpcc i8* @test_vst4q_s8_post(i8* %addr, %struct.int8x16x4_t %value.coerce) {
+; CHECK-LABEL: test_vst4q_s8_post:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: @ kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: vst40.8 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: vst41.8 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: vst42.8 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: vst43.8 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: adds r0, #64
+; CHECK-NEXT: bx lr
+entry:
+ %value.coerce.fca.0.0.extract = extractvalue %struct.int8x16x4_t %value.coerce, 0, 0
+ %value.coerce.fca.0.1.extract = extractvalue %struct.int8x16x4_t %value.coerce, 0, 1
+ %value.coerce.fca.0.2.extract = extractvalue %struct.int8x16x4_t %value.coerce, 0, 2
+ %value.coerce.fca.0.3.extract = extractvalue %struct.int8x16x4_t %value.coerce, 0, 3
+ tail call void @llvm.arm.mve.vst4q.p0i8.v16i8(i8* %addr, <16 x i8> %value.coerce.fca.0.0.extract, <16 x i8> %value.coerce.fca.0.1.extract, <16 x i8> %value.coerce.fca.0.2.extract, <16 x i8> %value.coerce.fca.0.3.extract, i32 0)
+ tail call void @llvm.arm.mve.vst4q.p0i8.v16i8(i8* %addr, <16 x i8> %value.coerce.fca.0.0.extract, <16 x i8> %value.coerce.fca.0.1.extract, <16 x i8> %value.coerce.fca.0.2.extract, <16 x i8> %value.coerce.fca.0.3.extract, i32 1)
+ tail call void @llvm.arm.mve.vst4q.p0i8.v16i8(i8* %addr, <16 x i8> %value.coerce.fca.0.0.extract, <16 x i8> %value.coerce.fca.0.1.extract, <16 x i8> %value.coerce.fca.0.2.extract, <16 x i8> %value.coerce.fca.0.3.extract, i32 2)
+ tail call void @llvm.arm.mve.vst4q.p0i8.v16i8(i8* %addr, <16 x i8> %value.coerce.fca.0.0.extract, <16 x i8> %value.coerce.fca.0.1.extract, <16 x i8> %value.coerce.fca.0.2.extract, <16 x i8> %value.coerce.fca.0.3.extract, i32 3)
+ %g = getelementptr i8, i8 *%addr, i32 64
+ ret i8* %g
+}
+
declare void @llvm.arm.mve.vst4q.p0i8.v16i8(i8*, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/Thumb2/mve-vld2-post.ll b/llvm/test/CodeGen/Thumb2/mve-vld2-post.ll
new file mode 100644
index 000000000000..cb8b42a86fa1
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/mve-vld2-post.ll
@@ -0,0 +1,173 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s
+
+; i32
+
+define <8 x i32> *@vld2_v4i32(<8 x i32> *%src, <4 x i32> *%dst) {
+; CHECK-LABEL: vld2_v4i32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vld20.32 {q0, q1}, [r0]
+; CHECK-NEXT: vld21.32 {q0, q1}, [r0]
+; CHECK-NEXT: adds r0, #32
+; CHECK-NEXT: vadd.i32 q0, q0, q1
+; CHECK-NEXT: vstrw.32 q0, [r1]
+; CHECK-NEXT: bx lr
+entry:
+ %l1 = load <8 x i32>, <8 x i32>* %src, align 4
+ %s1 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+ %s2 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+ %a = add <4 x i32> %s1, %s2
+ store <4 x i32> %a, <4 x i32> *%dst
+ %ret = getelementptr inbounds <8 x i32>, <8 x i32>* %src, i32 1
+ ret <8 x i32> *%ret
+}
+
+; i16
+
+define <16 x i16> *@vld2_v8i16(<16 x i16> *%src, <8 x i16> *%dst) {
+; CHECK-LABEL: vld2_v8i16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vld20.16 {q0, q1}, [r0]
+; CHECK-NEXT: vld21.16 {q0, q1}, [r0]
+; CHECK-NEXT: adds r0, #32
+; CHECK-NEXT: vadd.i16 q0, q0, q1
+; CHECK-NEXT: vstrw.32 q0, [r1]
+; CHECK-NEXT: bx lr
+entry:
+ %l1 = load <16 x i16>, <16 x i16>* %src, align 4
+ %s1 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+ %s2 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+ %a = add <8 x i16> %s1, %s2
+ store <8 x i16> %a, <8 x i16> *%dst
+ %ret = getelementptr inbounds <16 x i16>, <16 x i16>* %src, i32 1
+ ret <16 x i16> *%ret
+}
+
+; i8
+
+define <32 x i8> *@vld2_v16i8(<32 x i8> *%src, <16 x i8> *%dst) {
+; CHECK-LABEL: vld2_v16i8:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vld20.8 {q0, q1}, [r0]
+; CHECK-NEXT: vld21.8 {q0, q1}, [r0]
+; CHECK-NEXT: adds r0, #32
+; CHECK-NEXT: vadd.i8 q0, q0, q1
+; CHECK-NEXT: vstrw.32 q0, [r1]
+; CHECK-NEXT: bx lr
+entry:
+ %l1 = load <32 x i8>, <32 x i8>* %src, align 4
+ %s1 = shufflevector <32 x i8> %l1, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
+ %s2 = shufflevector <32 x i8> %l1, <32 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
+ %a = add <16 x i8> %s1, %s2
+ store <16 x i8> %a, <16 x i8> *%dst
+ %ret = getelementptr inbounds <32 x i8>, <32 x i8>* %src, i32 1
+ ret <32 x i8> *%ret
+}
+
+; i64
+
+define <4 x i64> *@vld2_v2i64(<4 x i64> *%src, <2 x i64> *%dst) {
+; CHECK-LABEL: vld2_v2i64:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r4, r5, r6, lr}
+; CHECK-NEXT: push {r4, r5, r6, lr}
+; CHECK-NEXT: vldrw.u32 q0, [r0]
+; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
+; CHECK-NEXT: adds r0, #32
+; CHECK-NEXT: vmov.f64 d2, d1
+; CHECK-NEXT: vmov.f32 s5, s3
+; CHECK-NEXT: vmov.f32 s6, s10
+; CHECK-NEXT: vmov.f32 s2, s8
+; CHECK-NEXT: vmov.f32 s7, s11
+; CHECK-NEXT: vmov.f32 s3, s9
+; CHECK-NEXT: vmov r2, s6
+; CHECK-NEXT: vmov r3, s2
+; CHECK-NEXT: vmov r4, s4
+; CHECK-NEXT: vmov r5, s0
+; CHECK-NEXT: vmov r12, s7
+; CHECK-NEXT: vmov lr, s3
+; CHECK-NEXT: adds r6, r3, r2
+; CHECK-NEXT: vmov r3, s5
+; CHECK-NEXT: vmov r2, s1
+; CHECK-NEXT: adc.w r12, r12, lr
+; CHECK-NEXT: adds r5, r5, r4
+; CHECK-NEXT: vmov.32 q0[0], r5
+; CHECK-NEXT: adcs r2, r3
+; CHECK-NEXT: vmov.32 q0[1], r2
+; CHECK-NEXT: vmov.32 q0[2], r6
+; CHECK-NEXT: vmov.32 q0[3], r12
+; CHECK-NEXT: vstrw.32 q0, [r1]
+; CHECK-NEXT: pop {r4, r5, r6, pc}
+entry:
+ %l1 = load <4 x i64>, <4 x i64>* %src, align 4
+ %s1 = shufflevector <4 x i64> %l1, <4 x i64> undef, <2 x i32> <i32 0, i32 2>
+ %s2 = shufflevector <4 x i64> %l1, <4 x i64> undef, <2 x i32> <i32 1, i32 3>
+ %a = add <2 x i64> %s1, %s2
+ store <2 x i64> %a, <2 x i64> *%dst
+ %ret = getelementptr inbounds <4 x i64>, <4 x i64>* %src, i32 1
+ ret <4 x i64> *%ret
+}
+
+; f32
+
+define <8 x float> *@vld2_v4f32(<8 x float> *%src, <4 x float> *%dst) {
+; CHECK-LABEL: vld2_v4f32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vld20.32 {q0, q1}, [r0]
+; CHECK-NEXT: vld21.32 {q0, q1}, [r0]
+; CHECK-NEXT: adds r0, #32
+; CHECK-NEXT: vadd.f32 q0, q0, q1
+; CHECK-NEXT: vstrw.32 q0, [r1]
+; CHECK-NEXT: bx lr
+entry:
+ %l1 = load <8 x float>, <8 x float>* %src, align 4
+ %s1 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+ %s2 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+ %a = fadd <4 x float> %s1, %s2
+ store <4 x float> %a, <4 x float> *%dst
+ %ret = getelementptr inbounds <8 x float>, <8 x float>* %src, i32 1
+ ret <8 x float> *%ret
+}
+
+; f16
+
+define <16 x half> *@vld2_v8f16(<16 x half> *%src, <8 x half> *%dst) {
+; CHECK-LABEL: vld2_v8f16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vld20.16 {q0, q1}, [r0]
+; CHECK-NEXT: vld21.16 {q0, q1}, [r0]
+; CHECK-NEXT: adds r0, #32
+; CHECK-NEXT: vadd.f16 q0, q0, q1
+; CHECK-NEXT: vstrw.32 q0, [r1]
+; CHECK-NEXT: bx lr
+entry:
+ %l1 = load <16 x half>, <16 x half>* %src, align 4
+ %s1 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+ %s2 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+ %a = fadd <8 x half> %s1, %s2
+ store <8 x half> %a, <8 x half> *%dst
+ %ret = getelementptr inbounds <16 x half>, <16 x half>* %src, i32 1
+ ret <16 x half> *%ret
+}
+
+; f64
+
+define <4 x double> *@vld2_v2f64(<4 x double> *%src, <2 x double> *%dst) {
+; CHECK-LABEL: vld2_v2f64:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
+; CHECK-NEXT: vldrw.u32 q1, [r0]
+; CHECK-NEXT: adds r0, #32
+; CHECK-NEXT: vadd.f64 d1, d0, d1
+; CHECK-NEXT: vadd.f64 d0, d2, d3
+; CHECK-NEXT: vstrw.32 q0, [r1]
+; CHECK-NEXT: bx lr
+entry:
+ %l1 = load <4 x double>, <4 x double>* %src, align 4
+ %s1 = shufflevector <4 x double> %l1, <4 x double> undef, <2 x i32> <i32 0, i32 2>
+ %s2 = shufflevector <4 x double> %l1, <4 x double> undef, <2 x i32> <i32 1, i32 3>
+ %a = fadd <2 x double> %s1, %s2
+ store <2 x double> %a, <2 x double> *%dst
+ %ret = getelementptr inbounds <4 x double>, <4 x double>* %src, i32 1
+ ret <4 x double> *%ret
+}
diff --git a/llvm/test/CodeGen/Thumb2/mve-vld4-post.ll b/llvm/test/CodeGen/Thumb2/mve-vld4-post.ll
new file mode 100644
index 000000000000..f6e3f4503525
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/mve-vld4-post.ll
@@ -0,0 +1,277 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s
+
+; i32
+
+define <16 x i32> *@vld4_v4i32(<16 x i32> *%src, <4 x i32> *%dst) {
+; CHECK-LABEL: vld4_v4i32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .vsave {d8, d9}
+; CHECK-NEXT: vpush {d8, d9}
+; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: adds r0, #64
+; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3
+; CHECK-NEXT: vadd.i32 q4, q2, q3
+; CHECK-NEXT: vadd.i32 q0, q0, q1
+; CHECK-NEXT: vadd.i32 q0, q0, q4
+; CHECK-NEXT: vstrw.32 q0, [r1]
+; CHECK-NEXT: vpop {d8, d9}
+; CHECK-NEXT: bx lr
+entry:
+ %l1 = load <16 x i32>, <16 x i32>* %src, align 4
+ %s1 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
+ %s2 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
+ %s3 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
+ %s4 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
+ %a1 = add <4 x i32> %s1, %s2
+ %a2 = add <4 x i32> %s3, %s4
+ %a3 = add <4 x i32> %a1, %a2
+ store <4 x i32> %a3, <4 x i32> *%dst
+ %ret = getelementptr inbounds <16 x i32>, <16 x i32>* %src, i32 1
+ ret <16 x i32> *%ret
+}
+
+; i16
+
+define <32 x i16> *@vld4_v8i16(<32 x i16> *%src, <8 x i16> *%dst) {
+; CHECK-LABEL: vld4_v8i16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .vsave {d8, d9}
+; CHECK-NEXT: vpush {d8, d9}
+; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: adds r0, #64
+; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3
+; CHECK-NEXT: vadd.i16 q4, q2, q3
+; CHECK-NEXT: vadd.i16 q0, q0, q1
+; CHECK-NEXT: vadd.i16 q0, q0, q4
+; CHECK-NEXT: vstrw.32 q0, [r1]
+; CHECK-NEXT: vpop {d8, d9}
+; CHECK-NEXT: bx lr
+entry:
+ %l1 = load <32 x i16>, <32 x i16>* %src, align 4
+ %s1 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
+ %s2 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>
+ %s3 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>
+ %s4 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>
+ %a1 = add <8 x i16> %s1, %s2
+ %a2 = add <8 x i16> %s3, %s4
+ %a3 = add <8 x i16> %a1, %a2
+ store <8 x i16> %a3, <8 x i16> *%dst
+ %ret = getelementptr inbounds <32 x i16>, <32 x i16>* %src, i32 1
+ ret <32 x i16> *%ret
+}
+
+; i8
+
+define <64 x i8> *@vld4_v16i8(<64 x i8> *%src, <16 x i8> *%dst) {
+; CHECK-LABEL: vld4_v16i8:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .vsave {d8, d9}
+; CHECK-NEXT: vpush {d8, d9}
+; CHECK-NEXT: vld40.8 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: vld41.8 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: vld42.8 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: vld43.8 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: adds r0, #64
+; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3
+; CHECK-NEXT: vadd.i8 q4, q2, q3
+; CHECK-NEXT: vadd.i8 q0, q0, q1
+; CHECK-NEXT: vadd.i8 q0, q0, q4
+; CHECK-NEXT: vstrw.32 q0, [r1]
+; CHECK-NEXT: vpop {d8, d9}
+; CHECK-NEXT: bx lr
+entry:
+ %l1 = load <64 x i8>, <64 x i8>* %src, align 4
+ %s1 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60>
+ %s2 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61>
+ %s3 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62>
+ %s4 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63>
+ %a1 = add <16 x i8> %s1, %s2
+ %a2 = add <16 x i8> %s3, %s4
+ %a3 = add <16 x i8> %a1, %a2
+ store <16 x i8> %a3, <16 x i8> *%dst
+ %ret = getelementptr inbounds <64 x i8>, <64 x i8>* %src, i32 1
+ ret <64 x i8> *%ret
+}
+
+; i64
+
+define <8 x i64> *@vld4_v2i64(<8 x i64> *%src, <2 x i64> *%dst) {
+; CHECK-LABEL: vld4_v2i64:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-NEXT: .pad #4
+; CHECK-NEXT: sub sp, #4
+; CHECK-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-NEXT: vldrw.u32 q3, [r0, #16]
+; CHECK-NEXT: vldrw.u32 q5, [r0, #48]
+; CHECK-NEXT: vldrw.u32 q0, [r0]
+; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
+; CHECK-NEXT: vmov.f64 d8, d7
+; CHECK-NEXT: adds r0, #64
+; CHECK-NEXT: vmov.f32 s17, s15
+; CHECK-NEXT: vmov.f32 s18, s22
+; CHECK-NEXT: vmov.f32 s14, s20
+; CHECK-NEXT: vmov.f32 s19, s23
+; CHECK-NEXT: vmov.f32 s15, s21
+; CHECK-NEXT: vmov r2, s18
+; CHECK-NEXT: vmov r3, s14
+; CHECK-NEXT: vmov.f64 d2, d1
+; CHECK-NEXT: vmov.f32 s5, s3
+; CHECK-NEXT: vmov.f32 s6, s10
+; CHECK-NEXT: vmov.f32 s2, s8
+; CHECK-NEXT: vmov.f32 s3, s9
+; CHECK-NEXT: vmov.f32 s7, s11
+; CHECK-NEXT: vmov r12, s19
+; CHECK-NEXT: vmov lr, s15
+; CHECK-NEXT: vmov r4, s6
+; CHECK-NEXT: vmov r5, s2
+; CHECK-NEXT: vmov r7, s0
+; CHECK-NEXT: adds r6, r3, r2
+; CHECK-NEXT: vmov r2, s7
+; CHECK-NEXT: vmov r3, s3
+; CHECK-NEXT: adc.w r12, r12, lr
+; CHECK-NEXT: adds r5, r5, r4
+; CHECK-NEXT: vmov r4, s16
+; CHECK-NEXT: adcs r2, r3
+; CHECK-NEXT: adds.w lr, r5, r6
+; CHECK-NEXT: adc.w r12, r12, r2
+; CHECK-NEXT: vmov r2, s12
+; CHECK-NEXT: vmov r6, s17
+; CHECK-NEXT: vmov r5, s13
+; CHECK-NEXT: vmov r3, s4
+; CHECK-NEXT: adds r2, r2, r4
+; CHECK-NEXT: vmov r4, s1
+; CHECK-NEXT: adcs r6, r5
+; CHECK-NEXT: vmov r5, s5
+; CHECK-NEXT: adds r3, r3, r7
+; CHECK-NEXT: adcs r4, r5
+; CHECK-NEXT: adds r2, r2, r3
+; CHECK-NEXT: adc.w r3, r4, r6
+; CHECK-NEXT: vmov.32 q0[0], r2
+; CHECK-NEXT: vmov.32 q0[1], r3
+; CHECK-NEXT: vmov.32 q0[2], lr
+; CHECK-NEXT: vmov.32 q0[3], r12
+; CHECK-NEXT: vstrw.32 q0, [r1]
+; CHECK-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-NEXT: add sp, #4
+; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
+entry:
+ %l1 = load <8 x i64>, <8 x i64>* %src, align 4
+ %s1 = shufflevector <8 x i64> %l1, <8 x i64> undef, <2 x i32> <i32 0, i32 4>
+ %s2 = shufflevector <8 x i64> %l1, <8 x i64> undef, <2 x i32> <i32 1, i32 5>
+ %s3 = shufflevector <8 x i64> %l1, <8 x i64> undef, <2 x i32> <i32 2, i32 6>
+ %s4 = shufflevector <8 x i64> %l1, <8 x i64> undef, <2 x i32> <i32 3, i32 7>
+ %a1 = add <2 x i64> %s1, %s2
+ %a2 = add <2 x i64> %s3, %s4
+ %a3 = add <2 x i64> %a1, %a2
+ store <2 x i64> %a3, <2 x i64> *%dst
+ %ret = getelementptr inbounds <8 x i64>, <8 x i64>* %src, i32 1
+ ret <8 x i64> *%ret
+}
+
+; f32
+
+define <16 x float> *@vld4_v4f32(<16 x float> *%src, <4 x float> *%dst) {
+; CHECK-LABEL: vld4_v4f32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .vsave {d8, d9}
+; CHECK-NEXT: vpush {d8, d9}
+; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: adds r0, #64
+; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3
+; CHECK-NEXT: vadd.f32 q4, q2, q3
+; CHECK-NEXT: vadd.f32 q0, q0, q1
+; CHECK-NEXT: vadd.f32 q0, q0, q4
+; CHECK-NEXT: vstrw.32 q0, [r1]
+; CHECK-NEXT: vpop {d8, d9}
+; CHECK-NEXT: bx lr
+entry:
+ %l1 = load <16 x float>, <16 x float>* %src, align 4
+ %s1 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
+ %s2 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
+ %s3 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
+ %s4 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
+ %a1 = fadd <4 x float> %s1, %s2
+ %a2 = fadd <4 x float> %s3, %s4
+ %a3 = fadd <4 x float> %a1, %a2
+ store <4 x float> %a3, <4 x float> *%dst
+ %ret = getelementptr inbounds <16 x float>, <16 x float>* %src, i32 1
+ ret <16 x float> *%ret
+}
+
+; f16
+
+define <32 x half> *@vld4_v8f16(<32 x half> *%src, <8 x half> *%dst) {
+; CHECK-LABEL: vld4_v8f16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .vsave {d8, d9}
+; CHECK-NEXT: vpush {d8, d9}
+; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0]
+; CHECK-NEXT: adds r0, #64
+; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3
+; CHECK-NEXT: vadd.f16 q4, q2, q3
+; CHECK-NEXT: vadd.f16 q0, q0, q1
+; CHECK-NEXT: vadd.f16 q0, q0, q4
+; CHECK-NEXT: vstrw.32 q0, [r1]
+; CHECK-NEXT: vpop {d8, d9}
+; CHECK-NEXT: bx lr
+entry:
+ %l1 = load <32 x half>, <32 x half>* %src, align 4
+ %s1 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
+ %s2 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>
+ %s3 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>
+ %s4 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>
+ %a1 = fadd <8 x half> %s1, %s2
+ %a2 = fadd <8 x half> %s3, %s4
+ %a3 = fadd <8 x half> %a1, %a2
+ store <8 x half> %a3, <8 x half> *%dst
+ %ret = getelementptr inbounds <32 x half>, <32 x half>* %src, i32 1
+ ret <32 x half> *%ret
+}
+
+; f64
+
+define <8 x double> *@vld4_v2f64(<8 x double> *%src, <2 x double> *%dst) {
+; CHECK-LABEL: vld4_v2f64:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vldrw.u32 q0, [r0, #48]
+; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
+; CHECK-NEXT: vldrw.u32 q2, [r0]
+; CHECK-NEXT: vadd.f64 d0, d0, d1
+; CHECK-NEXT: vadd.f64 d1, d2, d3
+; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
+; CHECK-NEXT: adds r0, #64
+; CHECK-NEXT: vadd.f64 d2, d2, d3
+; CHECK-NEXT: vadd.f64 d3, d4, d5
+; CHECK-NEXT: vadd.f64 d1, d1, d0
+; CHECK-NEXT: vadd.f64 d0, d3, d2
+; CHECK-NEXT: vstrw.32 q0, [r1]
+; CHECK-NEXT: bx lr
+entry:
+ %l1 = load <8 x double>, <8 x double>* %src, align 4
+ %s1 = shufflevector <8 x double> %l1, <8 x double> undef, <2 x i32> <i32 0, i32 4>
+ %s2 = shufflevector <8 x double> %l1, <8 x double> undef, <2 x i32> <i32 1, i32 5>
+ %s3 = shufflevector <8 x double> %l1, <8 x double> undef, <2 x i32> <i32 2, i32 6>
+ %s4 = shufflevector <8 x double> %l1, <8 x double> undef, <2 x i32> <i32 3, i32 7>
+ %a1 = fadd <2 x double> %s1, %s2
+ %a2 = fadd <2 x double> %s3, %s4
+ %a3 = fadd <2 x double> %a1, %a2
+ store <2 x double> %a3, <2 x double> *%dst
+ %ret = getelementptr inbounds <8 x double>, <8 x double>* %src, i32 1
+ ret <8 x double> *%ret
+}
diff --git a/llvm/test/CodeGen/Thumb2/mve-vst2-post.ll b/llvm/test/CodeGen/Thumb2/mve-vst2-post.ll
new file mode 100644
index 000000000000..56b8ab60c992
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/mve-vst2-post.ll
@@ -0,0 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s
+
+; i32
+
+define <8 x i32> *@vst2_v4i32(<4 x i32> *%src, <8 x i32> *%dst) {
+; CHECK-LABEL: vst2_v4i32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
+; CHECK-NEXT: vldrw.u32 q0, [r0]
+; CHECK-NEXT: add.w r0, r1, #32
+; CHECK-NEXT: vst20.32 {q0, q1}, [r1]
+; CHECK-NEXT: vst21.32 {q0, q1}, [r1]
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = getelementptr <4 x i32>, <4 x i32>* %src, i32 0
+ %l1 = load <4 x i32>, <4 x i32>* %s1, align 4
+ %s2 = getelementptr <4 x i32>, <4 x i32>* %src, i32 1
+ %l2 = load <4 x i32>, <4 x i32>* %s2, align 4
+ %s = shufflevector <4 x i32> %l1, <4 x i32> %l2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
+ store <8 x i32> %s, <8 x i32> *%dst
+ %ret = getelementptr inbounds <8 x i32>, <8 x i32>* %dst, i32 1
+ ret <8 x i32> *%ret
+}
+
+; i16
+
+define <16 x i16> *@vst2_v8i16(<8 x i16> *%src, <16 x i16> *%dst) {
+; CHECK-LABEL: vst2_v8i16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
+; CHECK-NEXT: vldrw.u32 q0, [r0]
+; CHECK-NEXT: add.w r0, r1, #32
+; CHECK-NEXT: vst20.16 {q0, q1}, [r1]
+; CHECK-NEXT: vst21.16 {q0, q1}, [r1]
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = getelementptr <8 x i16>, <8 x i16>* %src, i32 0
+ %l1 = load <8 x i16>, <8 x i16>* %s1, align 4
+ %s2 = getelementptr <8 x i16>, <8 x i16>* %src, i32 1
+ %l2 = load <8 x i16>, <8 x i16>* %s2, align 4
+ %s = shufflevector <8 x i16> %l1, <8 x i16> %l2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
+ store <16 x i16> %s, <16 x i16> *%dst
+ %ret = getelementptr inbounds <16 x i16>, <16 x i16>* %dst, i32 1
+ ret <16 x i16> *%ret
+}
+
+; i8
+
+define <32 x i8> *@vst2_v16i8(<16 x i8> *%src, <32 x i8> *%dst) {
+; CHECK-LABEL: vst2_v16i8:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
+; CHECK-NEXT: vldrw.u32 q0, [r0]
+; CHECK-NEXT: add.w r0, r1, #32
+; CHECK-NEXT: vst20.8 {q0, q1}, [r1]
+; CHECK-NEXT: vst21.8 {q0, q1}, [r1]
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = getelementptr <16 x i8>, <16 x i8>* %src, i32 0
+ %l1 = load <16 x i8>, <16 x i8>* %s1, align 4
+ %s2 = getelementptr <16 x i8>, <16 x i8>* %src, i32 1
+ %l2 = load <16 x i8>, <16 x i8>* %s2, align 4
+ %s = shufflevector <16 x i8> %l1, <16 x i8> %l2, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
+ store <32 x i8> %s, <32 x i8> *%dst
+ %ret = getelementptr inbounds <32 x i8>, <32 x i8>* %dst, i32 1
+ ret <32 x i8> *%ret
+}
+
+; i64
+
+define <4 x i64> *@vst2_v2i64(<2 x i64> *%src, <4 x i64> *%dst) {
+; CHECK-LABEL: vst2_v2i64:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vldrw.u32 q0, [r0]
+; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
+; CHECK-NEXT: add.w r0, r1, #32
+; CHECK-NEXT: vmov.f64 d4, d1
+; CHECK-NEXT: vmov.f32 s9, s3
+; CHECK-NEXT: vmov.f32 s2, s4
+; CHECK-NEXT: vmov.f32 s10, s6
+; CHECK-NEXT: vmov.f32 s3, s5
+; CHECK-NEXT: vmov.f32 s11, s7
+; CHECK-NEXT: vstrb.8 q0, [r1], #16
+; CHECK-NEXT: vstrw.32 q2, [r1]
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = getelementptr <2 x i64>, <2 x i64>* %src, i32 0
+ %l1 = load <2 x i64>, <2 x i64>* %s1, align 4
+ %s2 = getelementptr <2 x i64>, <2 x i64>* %src, i32 1
+ %l2 = load <2 x i64>, <2 x i64>* %s2, align 4
+ %s = shufflevector <2 x i64> %l1, <2 x i64> %l2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
+ store <4 x i64> %s, <4 x i64> *%dst
+ %ret = getelementptr inbounds <4 x i64>, <4 x i64>* %dst, i32 1
+ ret <4 x i64> *%ret
+}
+
+; f32
+
+define <8 x float> *@vst2_v4f32(<4 x float> *%src, <8 x float> *%dst) {
+; CHECK-LABEL: vst2_v4f32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
+; CHECK-NEXT: vldrw.u32 q0, [r0]
+; CHECK-NEXT: add.w r0, r1, #32
+; CHECK-NEXT: vst20.32 {q0, q1}, [r1]
+; CHECK-NEXT: vst21.32 {q0, q1}, [r1]
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = getelementptr <4 x float>, <4 x float>* %src, i32 0
+ %l1 = load <4 x float>, <4 x float>* %s1, align 4
+ %s2 = getelementptr <4 x float>, <4 x float>* %src, i32 1
+ %l2 = load <4 x float>, <4 x float>* %s2, align 4
+ %s = shufflevector <4 x float> %l1, <4 x float> %l2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
+ store <8 x float> %s, <8 x float> *%dst
+ %ret = getelementptr inbounds <8 x float>, <8 x float>* %dst, i32 1
+ ret <8 x float> *%ret
+}
+
+; f16
+
+define <16 x half> *@vst2_v8f16(<8 x half> *%src, <16 x half> *%dst) {
+; CHECK-LABEL: vst2_v8f16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
+; CHECK-NEXT: vldrw.u32 q0, [r0]
+; CHECK-NEXT: add.w r0, r1, #32
+; CHECK-NEXT: vst20.16 {q0, q1}, [r1]
+; CHECK-NEXT: vst21.16 {q0, q1}, [r1]
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = getelementptr <8 x half>, <8 x half>* %src, i32 0
+ %l1 = load <8 x half>, <8 x half>* %s1, align 4
+ %s2 = getelementptr <8 x half>, <8 x half>* %src, i32 1
+ %l2 = load <8 x half>, <8 x half>* %s2, align 4
+ %s = shufflevector <8 x half> %l1, <8 x half> %l2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
+ store <16 x half> %s, <16 x half> *%dst
+ %ret = getelementptr inbounds <16 x half>, <16 x half>* %dst, i32 1
+ ret <16 x half> *%ret
+}
+
+; f64
+
+define <4 x double> *@vst2_v2f64(<2 x double> *%src, <4 x double> *%dst) {
+; CHECK-LABEL: vst2_v2f64:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vldrw.u32 q1, [r0]
+; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
+; CHECK-NEXT: add.w r0, r1, #32
+; CHECK-NEXT: vmov.f64 d4, d2
+; CHECK-NEXT: vmov.f64 d5, d0
+; CHECK-NEXT: vmov.f64 d0, d3
+; CHECK-NEXT: vstrw.32 q2, [r1]
+; CHECK-NEXT: vstrw.32 q0, [r1, #16]
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = getelementptr <2 x double>, <2 x double>* %src, i32 0
+ %l1 = load <2 x double>, <2 x double>* %s1, align 4
+ %s2 = getelementptr <2 x double>, <2 x double>* %src, i32 1
+ %l2 = load <2 x double>, <2 x double>* %s2, align 4
+ %s = shufflevector <2 x double> %l1, <2 x double> %l2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
+ store <4 x double> %s, <4 x double> *%dst
+ %ret = getelementptr inbounds <4 x double>, <4 x double>* %dst, i32 1
+ ret <4 x double> *%ret
+}
diff --git a/llvm/test/CodeGen/Thumb2/mve-vst4-post.ll b/llvm/test/CodeGen/Thumb2/mve-vst4-post.ll
new file mode 100644
index 000000000000..ac326bc2f387
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/mve-vst4-post.ll
@@ -0,0 +1,250 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s
+
+; i32
+
+define <16 x i32> *@vst4_v4i32(<4 x i32> *%src, <16 x i32> *%dst) {
+; CHECK-LABEL: vst4_v4i32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
+; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
+; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
+; CHECK-NEXT: vldrw.u32 q0, [r0]
+; CHECK-NEXT: add.w r0, r1, #64
+; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r1]
+; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r1]
+; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r1]
+; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r1]
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = getelementptr <4 x i32>, <4 x i32>* %src, i32 0
+ %l1 = load <4 x i32>, <4 x i32>* %s1, align 4
+ %s2 = getelementptr <4 x i32>, <4 x i32>* %src, i32 1
+ %l2 = load <4 x i32>, <4 x i32>* %s2, align 4
+ %s3 = getelementptr <4 x i32>, <4 x i32>* %src, i32 2
+ %l3 = load <4 x i32>, <4 x i32>* %s3, align 4
+ %s4 = getelementptr <4 x i32>, <4 x i32>* %src, i32 3
+ %l4 = load <4 x i32>, <4 x i32>* %s4, align 4
+ %t1 = shufflevector <4 x i32> %l1, <4 x i32> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %t2 = shufflevector <4 x i32> %l3, <4 x i32> %l4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %s = shufflevector <8 x i32> %t1, <8 x i32> %t2, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
+ store <16 x i32> %s, <16 x i32> *%dst
+ %ret = getelementptr inbounds <16 x i32>, <16 x i32>* %dst, i32 1
+ ret <16 x i32> *%ret
+}
+
+; i16
+
+define <32 x i16> *@vst4_v8i16(<8 x i16> *%src, <32 x i16> *%dst) {
+; CHECK-LABEL: vst4_v8i16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
+; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
+; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
+; CHECK-NEXT: vldrw.u32 q0, [r0]
+; CHECK-NEXT: add.w r0, r1, #64
+; CHECK-NEXT: vst40.16 {q0, q1, q2, q3}, [r1]
+; CHECK-NEXT: vst41.16 {q0, q1, q2, q3}, [r1]
+; CHECK-NEXT: vst42.16 {q0, q1, q2, q3}, [r1]
+; CHECK-NEXT: vst43.16 {q0, q1, q2, q3}, [r1]
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = getelementptr <8 x i16>, <8 x i16>* %src, i32 0
+ %l1 = load <8 x i16>, <8 x i16>* %s1, align 4
+ %s2 = getelementptr <8 x i16>, <8 x i16>* %src, i32 1
+ %l2 = load <8 x i16>, <8 x i16>* %s2, align 4
+ %s3 = getelementptr <8 x i16>, <8 x i16>* %src, i32 2
+ %l3 = load <8 x i16>, <8 x i16>* %s3, align 4
+ %s4 = getelementptr <8 x i16>, <8 x i16>* %src, i32 3
+ %l4 = load <8 x i16>, <8 x i16>* %s4, align 4
+ %t1 = shufflevector <8 x i16> %l1, <8 x i16> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %t2 = shufflevector <8 x i16> %l3, <8 x i16> %l4, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %s = shufflevector <16 x i16> %t1, <16 x i16> %t2, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31>
+ store <32 x i16> %s, <32 x i16> *%dst
+ %ret = getelementptr inbounds <32 x i16>, <32 x i16>* %dst, i32 1
+ ret <32 x i16> *%ret
+}
+
+; i8
+
+define <64 x i8> *@vst4_v16i8(<16 x i8> *%src, <64 x i8> *%dst) {
+; CHECK-LABEL: vst4_v16i8:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
+; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
+; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
+; CHECK-NEXT: vldrw.u32 q0, [r0]
+; CHECK-NEXT: add.w r0, r1, #64
+; CHECK-NEXT: vst40.8 {q0, q1, q2, q3}, [r1]
+; CHECK-NEXT: vst41.8 {q0, q1, q2, q3}, [r1]
+; CHECK-NEXT: vst42.8 {q0, q1, q2, q3}, [r1]
+; CHECK-NEXT: vst43.8 {q0, q1, q2, q3}, [r1]
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = getelementptr <16 x i8>, <16 x i8>* %src, i32 0
+ %l1 = load <16 x i8>, <16 x i8>* %s1, align 4
+ %s2 = getelementptr <16 x i8>, <16 x i8>* %src, i32 1
+ %l2 = load <16 x i8>, <16 x i8>* %s2, align 4
+ %s3 = getelementptr <16 x i8>, <16 x i8>* %src, i32 2
+ %l3 = load <16 x i8>, <16 x i8>* %s3, align 4
+ %s4 = getelementptr <16 x i8>, <16 x i8>* %src, i32 3
+ %l4 = load <16 x i8>, <16 x i8>* %s4, align 4
+ %t1 = shufflevector <16 x i8> %l1, <16 x i8> %l2, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+ %t2 = shufflevector <16 x i8> %l3, <16 x i8> %l4, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+ %s = shufflevector <32 x i8> %t1, <32 x i8> %t2, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63>
+ store <64 x i8> %s, <64 x i8> *%dst
+ %ret = getelementptr inbounds <64 x i8>, <64 x i8>* %dst, i32 1
+ ret <64 x i8> *%ret
+}
+
+; i64
+
+define <8 x i64> *@vst4_v2i64(<2 x i64> *%src, <8 x i64> *%dst) {
+; CHECK-LABEL: vst4_v2i64:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .vsave {d8, d9}
+; CHECK-NEXT: vpush {d8, d9}
+; CHECK-NEXT: vldrw.u32 q4, [r0]
+; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
+; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
+; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
+; CHECK-NEXT: vmov.f64 d4, d8
+; CHECK-NEXT: add.w r0, r1, #64
+; CHECK-NEXT: vmov.f32 s9, s17
+; CHECK-NEXT: vmov.f32 s10, s0
+; CHECK-NEXT: vmov.f32 s11, s1
+; CHECK-NEXT: vmov.f32 s0, s18
+; CHECK-NEXT: vstrw.32 q2, [r1]
+; CHECK-NEXT: vmov.f32 s1, s19
+; CHECK-NEXT: vmov.f64 d8, d6
+; CHECK-NEXT: vstrw.32 q0, [r1, #32]
+; CHECK-NEXT: vmov.f32 s17, s13
+; CHECK-NEXT: vmov.f32 s18, s4
+; CHECK-NEXT: vmov.f32 s19, s5
+; CHECK-NEXT: vmov.f32 s4, s14
+; CHECK-NEXT: vstrw.32 q4, [r1, #16]
+; CHECK-NEXT: vmov.f32 s5, s15
+; CHECK-NEXT: vstrw.32 q1, [r1, #48]
+; CHECK-NEXT: vpop {d8, d9}
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = getelementptr <2 x i64>, <2 x i64>* %src, i32 0
+ %l1 = load <2 x i64>, <2 x i64>* %s1, align 4
+ %s2 = getelementptr <2 x i64>, <2 x i64>* %src, i32 1
+ %l2 = load <2 x i64>, <2 x i64>* %s2, align 4
+ %s3 = getelementptr <2 x i64>, <2 x i64>* %src, i32 2
+ %l3 = load <2 x i64>, <2 x i64>* %s3, align 4
+ %s4 = getelementptr <2 x i64>, <2 x i64>* %src, i32 3
+ %l4 = load <2 x i64>, <2 x i64>* %s4, align 4
+ %t1 = shufflevector <2 x i64> %l1, <2 x i64> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %t2 = shufflevector <2 x i64> %l3, <2 x i64> %l4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %s = shufflevector <4 x i64> %t1, <4 x i64> %t2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
+ store <8 x i64> %s, <8 x i64> *%dst
+ %ret = getelementptr inbounds <8 x i64>, <8 x i64>* %dst, i32 1
+ ret <8 x i64> *%ret
+}
+
+; f32
+
+define <16 x float> *@vst4_v4f32(<4 x float> *%src, <16 x float> *%dst) {
+; CHECK-LABEL: vst4_v4f32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
+; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
+; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
+; CHECK-NEXT: vldrw.u32 q0, [r0]
+; CHECK-NEXT: add.w r0, r1, #64
+; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r1]
+; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r1]
+; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r1]
+; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r1]
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = getelementptr <4 x float>, <4 x float>* %src, i32 0
+ %l1 = load <4 x float>, <4 x float>* %s1, align 4
+ %s2 = getelementptr <4 x float>, <4 x float>* %src, i32 1
+ %l2 = load <4 x float>, <4 x float>* %s2, align 4
+ %s3 = getelementptr <4 x float>, <4 x float>* %src, i32 2
+ %l3 = load <4 x float>, <4 x float>* %s3, align 4
+ %s4 = getelementptr <4 x float>, <4 x float>* %src, i32 3
+ %l4 = load <4 x float>, <4 x float>* %s4, align 4
+ %t1 = shufflevector <4 x float> %l1, <4 x float> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %t2 = shufflevector <4 x float> %l3, <4 x float> %l4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %s = shufflevector <8 x float> %t1, <8 x float> %t2, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
+ store <16 x float> %s, <16 x float> *%dst
+ %ret = getelementptr inbounds <16 x float>, <16 x float>* %dst, i32 1
+ ret <16 x float> *%ret
+}
+
+; f16
+
+define <32 x half> *@vst4_v8f16(<8 x half> *%src, <32 x half> *%dst) {
+; CHECK-LABEL: vst4_v8f16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
+; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
+; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
+; CHECK-NEXT: vldrw.u32 q0, [r0]
+; CHECK-NEXT: add.w r0, r1, #64
+; CHECK-NEXT: vst40.16 {q0, q1, q2, q3}, [r1]
+; CHECK-NEXT: vst41.16 {q0, q1, q2, q3}, [r1]
+; CHECK-NEXT: vst42.16 {q0, q1, q2, q3}, [r1]
+; CHECK-NEXT: vst43.16 {q0, q1, q2, q3}, [r1]
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = getelementptr <8 x half>, <8 x half>* %src, i32 0
+ %l1 = load <8 x half>, <8 x half>* %s1, align 4
+ %s2 = getelementptr <8 x half>, <8 x half>* %src, i32 1
+ %l2 = load <8 x half>, <8 x half>* %s2, align 4
+ %s3 = getelementptr <8 x half>, <8 x half>* %src, i32 2
+ %l3 = load <8 x half>, <8 x half>* %s3, align 4
+ %s4 = getelementptr <8 x half>, <8 x half>* %src, i32 3
+ %l4 = load <8 x half>, <8 x half>* %s4, align 4
+ %t1 = shufflevector <8 x half> %l1, <8 x half> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %t2 = shufflevector <8 x half> %l3, <8 x half> %l4, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %s = shufflevector <16 x half> %t1, <16 x half> %t2, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31>
+ store <32 x half> %s, <32 x half> *%dst
+ %ret = getelementptr inbounds <32 x half>, <32 x half>* %dst, i32 1
+ ret <32 x half> *%ret
+}
+
+; f64
+
+define <8 x double> *@vst4_v2f64(<2 x double> *%src, <8 x double> *%dst) {
+; CHECK-LABEL: vst4_v2f64:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .vsave {d8, d9}
+; CHECK-NEXT: vpush {d8, d9}
+; CHECK-NEXT: vldrw.u32 q3, [r0]
+; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
+; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
+; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
+; CHECK-NEXT: vmov.f64 d4, d6
+; CHECK-NEXT: add.w r0, r1, #64
+; CHECK-NEXT: vmov.f64 d5, d0
+; CHECK-NEXT: vmov.f64 d0, d7
+; CHECK-NEXT: vstrw.32 q2, [r1]
+; CHECK-NEXT: vmov.f64 d6, d8
+; CHECK-NEXT: vstrw.32 q0, [r1, #32]
+; CHECK-NEXT: vmov.f64 d7, d2
+; CHECK-NEXT: vmov.f64 d2, d9
+; CHECK-NEXT: vstrw.32 q3, [r1, #16]
+; CHECK-NEXT: vstrw.32 q1, [r1, #48]
+; CHECK-NEXT: vpop {d8, d9}
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = getelementptr <2 x double>, <2 x double>* %src, i32 0
+ %l1 = load <2 x double>, <2 x double>* %s1, align 4
+ %s2 = getelementptr <2 x double>, <2 x double>* %src, i32 1
+ %l2 = load <2 x double>, <2 x double>* %s2, align 4
+ %s3 = getelementptr <2 x double>, <2 x double>* %src, i32 2
+ %l3 = load <2 x double>, <2 x double>* %s3, align 4
+ %s4 = getelementptr <2 x double>, <2 x double>* %src, i32 3
+ %l4 = load <2 x double>, <2 x double>* %s4, align 4
+ %t1 = shufflevector <2 x double> %l1, <2 x double> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %t2 = shufflevector <2 x double> %l3, <2 x double> %l4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %s = shufflevector <4 x double> %t1, <4 x double> %t2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
+ store <8 x double> %s, <8 x double> *%dst
+ %ret = getelementptr inbounds <8 x double>, <8 x double>* %dst, i32 1
+ ret <8 x double> *%ret
+}
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