[PATCH] D72919: [AArch64] Add custom store lowering for 256 bit non-temporal stores.

[Florian Hahn via Phabricator via llvm-commits]

fhahn added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:2727
 
+def : Pat<(AArch64stnp FPR128:$Rt, FPR128:$Rt2, (am_indexed7s64 GPR64sp:$Rn, simm7s8:$offset)),
+          (STNPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, simm7s8:$offset)>;
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dmgreen wrote:
> Should this be simm7s16? Same for am_indexed7s128
Yes! I've updated that and now the offsets should be correct.


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Comment at: llvm/test/CodeGen/AArch64/nontemporal.ll:361
+; CHECK-NEXT:    stnp    d1, d2, [x0, #16]
+; CHECK-NEXT:    stnp    d0, d3, [x0]
+; CHECK-NEXT:    ret
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dmgreen wrote:
> Should halves work too?
Yes, I've added the missing handler for v16f16.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72919/new/

https://reviews.llvm.org/D72919