[PATCH] D72974: [mlir] Fix LLVM intrinsic convesion generator for overloadable types.

[River Riddle via Phabricator via llvm-commits]

rriddle added inline comments.


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Comment at: mlir/test/mlir-tblgen/llvm-intrinsics.td:9
 // processed and we only check the ouptut below.
+// we also verify emission of type specialization for overloadable intrinsics.
 //
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Start sentences with a capital letter.


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Comment at: mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp:34
 
+using IndicesTy = llvm::SmallVector<int, 4>;
+
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nit: Can you just use a SmallBitVector instead?


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Comment at: mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp:36
+
+/// Static free helper functions for accessing tablegen definitions.
+/// Return a CodeGen value type entry from a type record.
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nit: Remove this first line.


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Comment at: mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp:177
+  for (int idx : overloadedOps) {
+    os << "\n        opInst.getOpOperand(" << idx << ").get().getType()"
+       << ".cast<LLVM::LLVMType>().getUnderlyingType(),";
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Can you use getOperand instead?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72974/new/

https://reviews.llvm.org/D72974