[PATCH] D72944: [InstCombine] Fix worklist management when simplifying demanded bits (PR44541)

[Nikita Popov via Phabricator via llvm-commits]

nikic marked an inline comment as done.
nikic added inline comments.


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Comment at: llvm/test/Transforms/InstCombine/logical-select.ll:553
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <4 x i8> [[COND:%.*]], zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i8> [[TVAL:%.*]], <4 x i8> [[FVAL:%.*]]
 ; CHECK-NEXT:    ret <4 x i8> [[TMP2]]
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These changes are caused by https://bugs.llvm.org/show_bug.cgi?id=44521. It's one of two common spurious differences that arise when worklist order changes are made.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D72944/new/

https://reviews.llvm.org/D72944