[llvm] 49edf9a - [AArch64][SVE] Add break intrinsics
Cullen Rhodes via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 17 03:47:34 PST 2020
Author: Cullen Rhodes
Date: 2020-01-17T11:47:08Z
New Revision: 49edf9a509cd0dfccdb92e6a2661a55251d8182f
URL: https://github.com/llvm/llvm-project/commit/49edf9a509cd0dfccdb92e6a2661a55251d8182f
DIFF: https://github.com/llvm/llvm-project/commit/49edf9a509cd0dfccdb92e6a2661a55251d8182f.diff
LOG: [AArch64][SVE] Add break intrinsics
Summary:
Implements the following intrinsics:
* @llvm.aarch64.sve.brka
* @llvm.aarch64.sve.brka.z
* @llvm.aarch64.sve.brkb
* @llvm.aarch64.sve.brkb.z
* @llvm.aarch64.sve.brkn.z
* @llvm.aarch64.sve.brkpa.z
* @llvm.aarch64.sve.brkpb.z
Reviewers: sdesmalen, efriedma, dancgr, mgudim, cameron.mcinally, rengolin
Reviewed By: sdesmalen
Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72393
Added:
Modified:
llvm/include/llvm/IR/IntrinsicsAArch64.td
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/SVEInstrFormats.td
llvm/test/CodeGen/AArch64/sve-intrinsics-pred-operations.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index c72affeeec27..a5ac0a7b1c6c 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -1548,6 +1548,13 @@ def int_aarch64_sve_ptrue : AdvSIMD_SVE_PTRUE_Intrinsic;
def int_aarch64_sve_and_z : AdvSIMD_Pred2VectorArg_Intrinsic;
def int_aarch64_sve_bic_z : AdvSIMD_Pred2VectorArg_Intrinsic;
+def int_aarch64_sve_brka : AdvSIMD_Merged1VectorArg_Intrinsic;
+def int_aarch64_sve_brka_z : AdvSIMD_Pred1VectorArg_Intrinsic;
+def int_aarch64_sve_brkb : AdvSIMD_Merged1VectorArg_Intrinsic;
+def int_aarch64_sve_brkb_z : AdvSIMD_Pred1VectorArg_Intrinsic;
+def int_aarch64_sve_brkn_z : AdvSIMD_Pred2VectorArg_Intrinsic;
+def int_aarch64_sve_brkpa_z : AdvSIMD_Pred2VectorArg_Intrinsic;
+def int_aarch64_sve_brkpb_z : AdvSIMD_Pred2VectorArg_Intrinsic;
def int_aarch64_sve_eor_z : AdvSIMD_Pred2VectorArg_Intrinsic;
def int_aarch64_sve_nand_z : AdvSIMD_Pred2VectorArg_Intrinsic;
def int_aarch64_sve_nor_z : AdvSIMD_Pred2VectorArg_Intrinsic;
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index c849d7af9a40..bc00042c4680 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -290,20 +290,20 @@ let Predicates = [HasSVE] in {
def MOVPRFX_ZZ : sve_int_bin_cons_misc_0_c<0b00000001, "movprfx", ZPRAny>;
defm FEXPA_ZZ : sve_int_bin_cons_misc_0_c_fexpa<"fexpa", int_aarch64_sve_fexpa_x>;
- def BRKPA_PPzPP : sve_int_brkp<0b00, "brkpa">;
- def BRKPAS_PPzPP : sve_int_brkp<0b10, "brkpas">;
- def BRKPB_PPzPP : sve_int_brkp<0b01, "brkpb">;
- def BRKPBS_PPzPP : sve_int_brkp<0b11, "brkpbs">;
-
- def BRKN_PPzP : sve_int_brkn<0b0, "brkn">;
- def BRKNS_PPzP : sve_int_brkn<0b1, "brkns">;
-
- defm BRKA_PPzP : sve_int_break_z<0b000, "brka">;
- defm BRKA_PPmP : sve_int_break_m<0b001, "brka">;
- defm BRKAS_PPzP : sve_int_break_z<0b010, "brkas">;
- defm BRKB_PPzP : sve_int_break_z<0b100, "brkb">;
- defm BRKB_PPmP : sve_int_break_m<0b101, "brkb">;
- defm BRKBS_PPzP : sve_int_break_z<0b110, "brkbs">;
+ defm BRKPA_PPzPP : sve_int_brkp<0b00, "brkpa", int_aarch64_sve_brkpa_z>;
+ defm BRKPAS_PPzPP : sve_int_brkp<0b10, "brkpas", null_frag>;
+ defm BRKPB_PPzPP : sve_int_brkp<0b01, "brkpb", int_aarch64_sve_brkpb_z>;
+ defm BRKPBS_PPzPP : sve_int_brkp<0b11, "brkpbs", null_frag>;
+
+ defm BRKN_PPzP : sve_int_brkn<0b0, "brkn", int_aarch64_sve_brkn_z>;
+ defm BRKNS_PPzP : sve_int_brkn<0b1, "brkns", null_frag>;
+
+ defm BRKA_PPzP : sve_int_break_z<0b000, "brka", int_aarch64_sve_brka_z>;
+ defm BRKA_PPmP : sve_int_break_m<0b001, "brka", int_aarch64_sve_brka>;
+ defm BRKAS_PPzP : sve_int_break_z<0b010, "brkas", null_frag>;
+ defm BRKB_PPzP : sve_int_break_z<0b100, "brkb", int_aarch64_sve_brkb_z>;
+ defm BRKB_PPmP : sve_int_break_m<0b101, "brkb", int_aarch64_sve_brkb>;
+ defm BRKBS_PPzP : sve_int_break_z<0b110, "brkbs", null_frag>;
def PTEST_PP : sve_int_ptest<0b010000, "ptest">;
def PFALSE : sve_int_pfalse<0b000000, "pfalse">;
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 8b92ca84f8b7..717eff34d2e0 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -6600,6 +6600,12 @@ class sve_int_brkp<bits<2> opc, string asm>
let Defs = !if(!eq (opc{1}, 1), [NZCV], []);
}
+multiclass sve_int_brkp<bits<2> opc, string asm, SDPatternOperator op> {
+ def NAME : sve_int_brkp<opc, asm>;
+
+ def : SVE_3_Op_Pat<nxv16i1, op, nxv16i1, nxv16i1, nxv16i1, !cast<Instruction>(NAME)>;
+}
+
//===----------------------------------------------------------------------===//
// SVE Partition Break Group
@@ -6626,6 +6632,12 @@ class sve_int_brkn<bit S, string asm>
let Defs = !if(!eq (S, 0b1), [NZCV], []);
}
+multiclass sve_int_brkn<bits<1> opc, string asm, SDPatternOperator op> {
+ def NAME : sve_int_brkn<opc, asm>;
+
+ def : SVE_3_Op_Pat<nxv16i1, op, nxv16i1, nxv16i1, nxv16i1, !cast<Instruction>(NAME)>;
+}
+
class sve_int_break<bits<3> opc, string asm, string suffix, dag iops>
: I<(outs PPR8:$Pd), iops,
asm, "\t$Pd, $Pg"#suffix#", $Pn",
@@ -6648,12 +6660,16 @@ class sve_int_break<bits<3> opc, string asm, string suffix, dag iops>
}
-multiclass sve_int_break_m<bits<3> opc, string asm> {
+multiclass sve_int_break_m<bits<3> opc, string asm, SDPatternOperator op> {
def NAME : sve_int_break<opc, asm, "/m", (ins PPR8:$_Pd, PPRAny:$Pg, PPR8:$Pn)>;
+
+ def : SVE_3_Op_Pat<nxv16i1, op, nxv16i1, nxv16i1, nxv16i1, !cast<Instruction>(NAME)>;
}
-multiclass sve_int_break_z<bits<3> opc, string asm> {
+multiclass sve_int_break_z<bits<3> opc, string asm, SDPatternOperator op> {
def NAME : sve_int_break<opc, asm, "/z", (ins PPRAny:$Pg, PPR8:$Pn)>;
+
+ def : SVE_2_Op_Pat<nxv16i1, op, nxv16i1, nxv16i1, !cast<Instruction>(NAME)>;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-pred-operations.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-pred-operations.ll
index cf7a8dc7908c..d167e95ff551 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-pred-operations.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-pred-operations.ll
@@ -1,5 +1,94 @@
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+;
+; BRKA
+;
+
+define <vscale x 16 x i1> @brka_m_b8(<vscale x 16 x i1> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
+; CHECK-LABEL: brka_m_b8:
+; CHECK: brka p0.b, p1/m, p2.b
+; CHECK-NEXT: ret
+ %out = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.nxv16i1(<vscale x 16 x i1> %inactive,
+ <vscale x 16 x i1> %pg,
+ <vscale x 16 x i1> %a)
+ ret <vscale x 16 x i1> %out
+}
+
+define <vscale x 16 x i1> @brka_z_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
+; CHECK-LABEL: brka_z_b8:
+; CHECK: brka p0.b, p0/z, p1.b
+; CHECK-NEXT: ret
+ %out = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1> %pg,
+ <vscale x 16 x i1> %a)
+ ret <vscale x 16 x i1> %out
+}
+
+;
+; BRKB
+;
+
+define <vscale x 16 x i1> @brkb_m_b8(<vscale x 16 x i1> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
+; CHECK-LABEL: brkb_m_b8:
+; CHECK: brkb p0.b, p1/m, p2.b
+; CHECK-NEXT: ret
+ %out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.nxv16i1(<vscale x 16 x i1> %inactive,
+ <vscale x 16 x i1> %pg,
+ <vscale x 16 x i1> %a)
+ ret <vscale x 16 x i1> %out
+}
+
+define <vscale x 16 x i1> @brkb_z_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
+; CHECK-LABEL: brkb_z_b8:
+; CHECK: brkb p0.b, p0/z, p1.b
+; CHECK-NEXT: ret
+ %out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1> %pg,
+ <vscale x 16 x i1> %a)
+ ret <vscale x 16 x i1> %out
+}
+
+;
+; BRKN
+;
+
+define <vscale x 16 x i1> @brkn_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: brkn_b8:
+; CHECK: brkn p2.b, p0/z, p1.b, p2.b
+; CHECK-NEXT: mov p0.b, p2.b
+; CHECK-NEXT: ret
+ %out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1> %pg,
+ <vscale x 16 x i1> %a,
+ <vscale x 16 x i1> %b)
+ ret <vscale x 16 x i1> %out
+}
+
+;
+; BRKPA
+;
+
+define <vscale x 16 x i1> @brkpa_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: brkpa_b8:
+; CHECK: brkpa p0.b, p0/z, p1.b, p2.b
+; CHECK-NEXT: ret
+ %out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1> %pg,
+ <vscale x 16 x i1> %a,
+ <vscale x 16 x i1> %b)
+ ret <vscale x 16 x i1> %out
+}
+
+;
+; BRKPB
+;
+
+define <vscale x 16 x i1> @brkpb_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: brkpb_b8:
+; CHECK: brkpb p0.b, p0/z, p1.b, p2.b
+; CHECK-NEXT: ret
+ %out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1> %pg,
+ <vscale x 16 x i1> %a,
+ <vscale x 16 x i1> %b)
+ ret <vscale x 16 x i1> %out
+}
+
;
; PFIRST
;
@@ -114,6 +203,14 @@ define <vscale x 2 x i1> @punpklo_b4(<vscale x 4 x i1> %a) {
ret <vscale x 2 x i1> %res
}
+declare <vscale x 16 x i1> @llvm.aarch64.sve.brka.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
+declare <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
+declare <vscale x 16 x i1> @llvm.aarch64.sve.brkb.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
+declare <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
+declare <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
+declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
+declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
+
declare <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
declare <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
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