[PATCH] D72569: [PowerPC][Future] Add prefixed instruction paddi to future CPU

[Amy Kwan via Phabricator via llvm-commits]

amyk added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCInstrFormats.td:48
+
+  // Inidicate that this instruction is prefixed.
+  bits<1> Prefixed = 0;
----------------
s/Inidicate/Indicate


================
Comment at: llvm/lib/Target/PowerPC/PPCScheduleP9.td:44
   // Do not support QPX (Quad Processing eXtension) or SPE (Signal Procesing
   // Engine) on Power 9.
+  let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs];
----------------
Perhaps we should also update the comment to include `PrefixInstrs`.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72569/new/

https://reviews.llvm.org/D72569