[PATCH] D65653: [AArch64] Change location of frame-record within callee-save area.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

> So I believe that after this change, we are no longer guaranteed that FP + 16 = SP at exit, correct?

Yes.

> I think this would be a requirement for a "fast" unwinder that works by following frame pointers (rather than reading unwind info) and is capable of decrypting return addresses of functions built with -msign-return-addresses (because the AUT instruction would need to know SP at exit).

Exception handling has to use a DWARF unwinder, not a "fast" unwinder. So the "fast" unwinder can't actually do anything with the address other than print it out.  Given that, I can't think of any security benefit to verifying the signature.  (And if you don't care about security, you can "decrypt" an address by just clearing the signing bits.)

> I'm not very familiar with SVE, but I would imagine that you could use a different register for this purpose on opted out platforms.

The point of the layout change is so the frame pointer points at the beginning of the scalable section of the stack frame.  This isn't strictly necessary; stack lowering should do the right thing anyway.  It just makes address computation a little faster (because we can just compute "fp+vscale*scaledoffset", instead of "fp+fixedoffset+vscale*scaledoffset").


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  https://reviews.llvm.org/D65653/new/

https://reviews.llvm.org/D65653