[PATCH] D70072: [ARM] Improve codegen of volatile load/store of i64

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Apparently the ARM-mode LDRD is a bit more strange than I realized.  From the ARM manual: `if t2 == 15 || m == 15 || m == t || m == t2 then UNPREDICTABLE;`.  I guess we're managed to avoid running into this in the past by never generating the register form of ldrd.

It should be possible to express this constraint to the register allocator using `@earlyclobber`.  (`@earlyclobber` is actually a little more conservative than we need, strictly speaking, but the difference probably doesn't matter too much.)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70072/new/

https://reviews.llvm.org/D70072