[PATCH] D72853: [GlobalISel] Don't arbitrarily limit a mask to 64 bits
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 16 07:59:50 PST 2020
foad created this revision.
foad added a reviewer: arsenm.
Herald added subscribers: Petar.Avramovic, volkan, hiraditya, rovka, wdng.
Herald added a project: LLVM.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D72853
Files:
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Index: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -1436,9 +1436,10 @@
// Do the arithmetic in the larger type.
auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
- APInt Mask = APInt::getAllOnesValue(OrigTy.getSizeInBits());
+ APInt Mask =
+ APInt::getLowBitsSet(WideTy.getSizeInBits(), OrigTy.getSizeInBits());
auto AndOp = MIRBuilder.buildAnd(
- WideTy, NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue()));
+ WideTy, NewOp, MIRBuilder.buildConstant(WideTy, Mask));
// There is no overflow if the AndOp is the same as NewOp.
MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp,
AndOp);
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D72853.238504.patch
Type: text/x-patch
Size: 956 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200116/92c5104c/attachment.bin>
More information about the llvm-commits
mailing list