[PATCH] D72831: [llvm-mc] - Produce R_X86_64_PLT32 relocation for branches with JCC opcodes too.

[George Rimar via Phabricator via llvm-commits]

grimar created this revision.
grimar added reviewers: craig.topper, MaskRay, ruiu.
Herald added subscribers: hiraditya, emaste.
Herald added a reviewer: espindola.
Herald added a project: LLVM.

The idea is to produce R_X86_64_PLT32 instead of
R_X86_64_PC32 for branches.

It fixes https://bugs.llvm.org/show_bug.cgi?id=44397.

This patch teaches MC to do that for JCC (jump if condition is met)
instructions. The new behavior matches modern GNU as.
It is similar to D43383 <https://reviews.llvm.org/D43383>, which did the same for "call/jmp foo",
but missed JCC cases.


https://reviews.llvm.org/D72831

Files:
  llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
  llvm/test/MC/ELF/basic-elf-64.s


Index: llvm/test/MC/ELF/basic-elf-64.s
===================================================================
--- llvm/test/MC/ELF/basic-elf-64.s
+++ llvm/test/MC/ELF/basic-elf-64.s
@@ -14,6 +14,37 @@
 	xorl	%eax, %eax
 	addq	$8, %rsp
     call foo at GOTPCREL
+    ja foo
+    jae foo
+    jb foo
+    jbe foo
+    jc foo
+    je foo
+    jz foo
+    jg foo
+    jge foo
+    jl foo
+    jle foo
+    jna foo
+    jnae foo
+    jnb foo
+    jnbe foo
+    jnc foo
+    jne foo
+    jng foo
+    jnge foo
+    jnl foo
+    jnle foo
+    jno foo
+    jnp foo
+    jns foo
+    jnz foo
+    jo foo
+    jp foo
+    jpe foo
+    jpo foo
+    js foo
+    jz foo
 	ret
 .Ltmp0:
 	.size	main, .Ltmp0-main
@@ -52,6 +83,37 @@
 // CHECK-NEXT:     0xF  R_X86_64_32   .rodata.str1.1 0x6
 // CHECK-NEXT:     0x14 R_X86_64_PLT32 puts           0xFFFFFFFFFFFFFFFC
 // CHECK-NEXT:     0x1F R_X86_64_GOTPCREL foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0x25 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0x2B R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0x31 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0x37 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0x3D R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0x43 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0x49 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0x4F R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0x55 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0x5B R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0x61 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0x67 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0x6D R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0x73 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0x79 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0x7F R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0x85 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0x8B R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0x91 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0x97 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0x9D R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0xA3 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0xA9 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0xAF R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0xB5 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0xBB R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0xC1 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0xC7 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0xCD R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0xD3 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+// CHECK-NEXT:     0xD9 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
 // CHECK-NEXT:   }
 // CHECK-NEXT: ]
 
Index: llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
===================================================================
--- llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -275,7 +275,8 @@
 static bool isPCRel32Branch(const MCInst &MI, const MCInstrInfo &MCII) {
   unsigned Opcode = MI.getOpcode();
   const MCInstrDesc &Desc = MCII.get(Opcode);
-  if ((Opcode != X86::CALL64pcrel32 && Opcode != X86::JMP_4) ||
+  if ((Opcode != X86::CALL64pcrel32 && Opcode != X86::JMP_4 &&
+       Opcode != X86::JCC_4) ||
       getImmFixupKind(Desc.TSFlags) != FK_PCRel_4)
     return false;
 


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