[PATCH] D68685: [RISCV] Scheduler description for Rocket Core
Hsiangkai Wang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 15 06:58:00 PST 2020
HsiangKai marked an inline comment as done.
HsiangKai added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVSchedule.td:105
+def ReadIM : SchedRead; // 32 & 64-bit multiply
+def ReadID : SchedRead; // 32 & 64-bit divide
----------------
lenary wrote:
> HsiangKai wrote:
> > shiva0217 wrote:
> > > HsiangKai wrote:
> > > > They are the only two SchedRead definitions. However, there is no place using them. I think you should specify more SchedRead types and associate these SchedRead to input operands in instruction definitions.
> > > Will the SchedRead for input operands be added, so they could be used by ReadAdvance to describe forwarding rules?
> > I also think so. I will add SchedRead for input operands.
> I presume this patch is not yet ready to land because it is still missing `SchedRead` for most input operands? Do you expect to have those ready before the LLVM 10.0 branch?
I will add SchedRead for input operands for these two days.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D68685/new/
https://reviews.llvm.org/D68685
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