[PATCH] D71338: [VE,#1] Scalar code generation

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/VE/VERegisterInfo.cpp:89
 
+  // Also reserve the register pair aliases covering the above
+  // registers, with the same conditions.  This is required since
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I recommend using the MCRegAliasIterator to do this, see AMDGPURegisterInfo::reserveRegisterTuples


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  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D71338/new/

https://reviews.llvm.org/D71338