[PATCH] D71773: [AArch64][SVE] Update the definition of AdvSIMD_GatherLoad_VecTorBase_Intrinsic

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

This makes sense.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:12207
+  // offsets use GLD1 or GLD1_UXTW instead.
+  if (Opcode == AArch64ISD::GLD1_IMM && !isa<ConstantSDNode>(Offset.getNode())) {
+    if (MVT::nxv4i32 == Base.getValueType().getSimpleVT().SimpleTy)
----------------
Do you need to handle the possibility that Offset is an immediate, but can't be encoded into a GLD1_IMM?


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  https://reviews.llvm.org/D71773/new/

https://reviews.llvm.org/D71773