[PATCH] D72740: [SLP] Don't allow Div/Rem as alternate opcodes

[Alexey Bataev via Phabricator via llvm-commits]

ABataev added inline comments.


================
Comment at: llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp:386
+static bool isValidForAlternation(unsigned Opcode) {
+  if (Instruction::isIntDivRem(Opcode))
+    return false;
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a.elovikov wrote:
> ABataev wrote:
> > What about float point ops?
> FP subclasses of llvm::Instruction rely on default floating point environment, so shouldn't throw. If FP operation can produce a signaling NaN it should be represented as constrained intrinsic (via CallInst), which I doubt is handled in this file and should probably bailout for other reasons earlier. At least, I don't see calls to TLI->isFunctionVectorizable in this file.
> 
> As such, I'm not aware of any existing issues in this regard. I'll be happy to update the code if you can point me which ones aren't valid and why.
I was just asking if you're sure about it - fine.


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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72740/new/

https://reviews.llvm.org/D72740