[PATCH] D72740: [SLP] Don't allow Div/Rem as alternate opcodes

[Andrei Elovikov via Phabricator via llvm-commits]

a.elovikov marked an inline comment as done.
a.elovikov added inline comments.


================
Comment at: llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp:414
         continue;
-      if (Opcode == AltOpcode) {
+      if (Opcode == AltOpcode && isValidForAlternation(InstOpcode) &&
+          isValidForAlternation(Opcode)) {
----------------
vporpo wrote:
> Does this cover the case where VL[0] is invalid? Maybe add a test for it?
I believe the second function in the LIT test verifies that - I have urem in the index 0 there.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D72740/new/

https://reviews.llvm.org/D72740