[PATCH] D72709: [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU.

[Michael Liao via Phabricator via llvm-commits]

hliao marked 2 inline comments as done.
hliao added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/dead-mi-use-same-intr.mir:17
   %1 = IMPLICIT_DEF
-  dead %2:vgpr_32 = V_MAC_F32_e32 %0:vgpr_32, %1:vgpr_32, undef %2:vgpr_32, implicit $exec
+  dead %3:vgpr_32 = V_MAC_F32_e32 %0:vgpr_32, %1:vgpr_32, undef %2:vgpr_32, implicit $exec
   S_ENDPGM 0
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rampitec wrote:
> The test became useless. The point was to check def of the same reg as use in the same instruction past SSA.
`dead-mi-elimination` only works for SSA form. If we really need a DIE for non-SSA MIR, we need to check dead def with live range.


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Comment at: llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll:249
 ; GCN:    NumVgprs: 256
-; GFX900: ScratchSize: 580
+; GFX900: ScratchSize: 644
 ; GFX908-FIXME: ScratchSize: 0
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rampitec wrote:
> That seem to affect register pressure quite badly. Register numbering in other places suggests other places are negatively affected too.
I have checked what causes the register pressure, yet. The changes in other places show register pressure is increased at the beginning but released earlier than the previous assignment. It's difficult to say which is good or bad. But, in general, except this spilling case, all other cases have no extra register requirements.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72709/new/

https://reviews.llvm.org/D72709