[PATCH] D72725: TableGen/GlobalISel: Don't reconstruct CodeGenRegBank
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 14 11:03:27 PST 2020
arsenm created this revision.
arsenm added reviewers: dsanders, paquette, aemerson, aditya_nandakumar.
Herald added subscribers: Petar.Avramovic, rovka, wdng.
Herald added a project: LLVM.
The maps for dealing with the relationships between different register
classes and subregister indexes rely on unique pointers for every
class/index. By constructing a second copy of CodeGenRegBank, two
different pointer values existed for a given subregister depending on
where you were querying.
Use the existing CodeGenRegBank owned by the CodeGenTarget instead of
constructing a second copy. This avoids incorrectly failing map
lookups in a future change.
https://reviews.llvm.org/D72725
Files:
llvm/utils/TableGen/GlobalISelEmitter.cpp
Index: llvm/utils/TableGen/GlobalISelEmitter.cpp
===================================================================
--- llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -3269,7 +3269,7 @@
const RecordKeeper &RK;
const CodeGenDAGPatterns CGP;
const CodeGenTarget &Target;
- CodeGenRegBank CGRegs;
+ CodeGenRegBank &CGRegs;
/// Keep track of the equivalence between SDNodes and Instruction by mapping
/// SDNodes to the GINodeEquiv mapping. We need to map to the GINodeEquiv to
@@ -3477,7 +3477,7 @@
GlobalISelEmitter::GlobalISelEmitter(RecordKeeper &RK)
: RK(RK), CGP(RK), Target(CGP.getTargetInfo()),
- CGRegs(RK, Target.getHwModes()) {}
+ CGRegs(Target.getRegBank()) {}
//===- Emitter ------------------------------------------------------------===//
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