[PATCH] D72709: [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU.

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

You have skipped the dead MO, but was pass reordering really necessary? It seems we have higher register pressure with this change.



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Comment at: llvm/test/CodeGen/AMDGPU/dead-mi-use-same-intr.mir:17
   %1 = IMPLICIT_DEF
-  dead %2:vgpr_32 = V_MAC_F32_e32 %0:vgpr_32, %1:vgpr_32, undef %2:vgpr_32, implicit $exec
+  dead %3:vgpr_32 = V_MAC_F32_e32 %0:vgpr_32, %1:vgpr_32, undef %2:vgpr_32, implicit $exec
   S_ENDPGM 0
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The test became useless. The point was to check def of the same reg as use in the same instruction past SSA.


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Comment at: llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll:249
 ; GCN:    NumVgprs: 256
-; GFX900: ScratchSize: 580
+; GFX900: ScratchSize: 644
 ; GFX908-FIXME: ScratchSize: 0
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That seem to affect register pressure quite badly. Register numbering in other places suggests other places are negatively affected too.


Repository:
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  https://reviews.llvm.org/D72709/new/

https://reviews.llvm.org/D72709