[PATCH] D72709: [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU.

[Michael Liao via Phabricator via llvm-commits]

hliao created this revision.
hliao added reviewers: rampitec, qcolombet, sunfish.
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Comment at: llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll:1
+; RUN: llc -march=amdgcn -verify-machineinstrs %s -o - | FileCheck %s
+
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This is the new test exposing the previous issue due to running MIR DIE after DeSSA. It results in illegal MIR.


- `dead-mi-elimination` assumes MIR in the SSA form and cannot be arranged after phi elimination or DeSSA. It's enhanced to handle the dead register definition by skipping use check on it. Once a register def is `dead`, all its uses, if any, should be `undef`.
- Re-arrange the DIE in RA phase for AMDGPU by placing it directly after `detect-dead-lanes`.
- Many relevant tests are refined due to different register assignment.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D72709

Files:
  llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
  llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
  llvm/test/CodeGen/AMDGPU/bswap.ll
  llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
  llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll
  llvm/test/CodeGen/AMDGPU/dead-mi-use-same-intr.mir
  llvm/test/CodeGen/AMDGPU/idot8u.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll
  llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
  llvm/test/CodeGen/AMDGPU/loop_break.ll
  llvm/test/CodeGen/AMDGPU/select.f16.ll
  llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll

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