[PATCH] D72509: [ARM][LowOverheadLoops] Allow all MVE instrs.

[Sam Parker via Phabricator via llvm-commits]

samparker marked an inline comment as done.
samparker added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp:525
+  if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
+    return true;
+
----------------
dmgreen wrote:
> samparker wrote:
> > dmgreen wrote:
> > > What if we had something like a `VMOV s0 s1`. I know that's not anything to do with this patch, but is that outlawed anywhere at the moment?
> > It's not outlawed., why do we need to be concerned about it?
> If we did `VMOV s7, s0; VMOV s6, s1; VMOV s5, s2; VMOV s4, s3`, that would be a reverse shuffle of a i32 vector. I would presume that would be trouble for tail prediction as it can no longer really be sure about what lanes are and are not predicated.
The conversion has to be about predication conversion, just making sure that it is equivalent, so these shouldn't be a problem. What needs to happen though is checking for values live in and out.... and then checking whether these scalar regs are aliasing the Q regs. I'm currently working on this.


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  https://reviews.llvm.org/D72509/new/

https://reviews.llvm.org/D72509